Author Topic: Wien Bridge project  (Read 11182 times)

0 Members and 1 Guest are viewing this topic.

Offline richlooker

  • Regular Contributor
  • *
  • Posts: 104
  • Country: no
Re: Wien Bridge project
« Reply #125 on: April 24, 2021, 10:36:20 pm »
The LT1006 is precision single supply, effectively a precision 324/358.  The LT1028 is fast precision low noise.  The LT1022 is fast low input bias current but since it is inverting, its common mode rejection is not important; it is suppressing common mode operation of the LT1028.  The LT1010 could be replaced by a diamond buffer.

I never understood why the LT1022 was used instead of another LT1028, but it was the fastest JFET part LT made at the time.  The newer and faster LT1122 should work as an improved replacement.

It has been so long that I have looked at it, 20+ years, that I forgot that, and forgot that I had a plan to get around it by making the JFET gain control floating.  But you are correct, that is obviously why Jim Williams did it that way.

Incidentally, I was looking at the LT1122 datasheet and they do recommend it as an improved replacement for the LT1022 in this application.

And I am sure someone else mentioned it but I will again, figures 47 and 48 are swapped in the application note.

I have these opamps at my disposal: LM4671/LM4672, NE5532, TL072, LT1253, LM837
 

Offline David Hess

  • Super Contributor
  • ***
  • Posts: 13101
  • Country: us
  • DavidH
Re: Wien Bridge project
« Reply #126 on: April 24, 2021, 11:04:42 pm »
I have not figured out how to make the JFET VGC floating, but I would be more than happy to achieve the 0.0018% THD Williams did with ground-referenced VGC.

It comes down to doing exactly what you might suspect, bootstrapping the gate signal to follow the input.  Examples are difficult to find on the internet because it is found in old circuits.

A pair of operational transcendence amplifiers can also do it.

I have these opamps at my disposal: LM4671/LM4672, NE5532, TL072, LT1253, LM837

LT1028 - NE5532 or LM837
LT1022 - TL072
LT1006 - TL072 but with negative supply
LT1010 - Discrete diamond buffer

You can still buy CdS photocells so get one and make the linear optocoupler with some black heat shrink tubing and an LED or bulb.

Or for the JFET version of Jim William's circuit:

LT1115 - NE5532 or LM837
LT1055 - TL072

Now I have to wonder why he replaced the LT1115 with the LT1028.  Were two different projects from different times combined into one application note?
 

Offline richlooker

  • Regular Contributor
  • *
  • Posts: 104
  • Country: no
Re: Wien Bridge project
« Reply #127 on: April 24, 2021, 11:07:04 pm »
This is the circuit from https://sound-au.com/project174.htm



And this is the result:

 

Offline richlooker

  • Regular Contributor
  • *
  • Posts: 104
  • Country: no
Re: Wien Bridge project
« Reply #128 on: April 24, 2021, 11:16:07 pm »

I have these opamps at my disposal: LM4671/LM4672, NE5532, TL072, LT1253, LM837

LT1028 - NE5532 or LM837
LT1022 - TL072
LT1006 - TL072 but with negative supply
LT1010 - Discrete diamond buffer

You can still buy CdS photocells so get one and make the linear optocoupler with some black heat shrink tubing and an LED or bulb.

Or for the JFET version of Jim William's circuit:

LT1115 - NE5532 or LM837
LT1055 - TL072

Now I have to wonder why he replaced the LT1115 with the LT1028.  Were two different projects from different times combined into one application note?

I have made an optocoupler like this: https://sound-au.com/project200.htm

And I made a typo - I meant LM6171/LM6172 (not LM4671/LM4672)

Discrete diamond buffer? Won't an LM6171 do?
 

Offline David Hess

  • Super Contributor
  • ***
  • Posts: 13101
  • Country: us
  • DavidH
Re: Wien Bridge project
« Reply #129 on: April 25, 2021, 12:23:08 am »
And I made a typo - I meant LM6171/LM6172 (not LM4671/LM4672)

I do not think the LM6171 will work as well as the NE5532 or LM837 because of lower open loop gain and precision as a replacement for the LT1028 or LT1115, but try it.

Quote
Discrete diamond buffer? Won't an LM6171 do?

The LM6171 might not need it because it has lower precision anyway but better operational amplifiers benefit from using an output buffer to prevent thermal feedback from their output stage to their input stage.  The LM6171 might be suitable as a replacement for the LT1010 or diamond buffer though.  It could also be used as part of a composite amplifier in a super gain block like the Linear Technology part-per-billion oscillator.
« Last Edit: April 25, 2021, 12:27:32 am by David Hess »
 

Online Kleinstein

  • Super Contributor
  • ***
  • Posts: 9216
  • Country: de
Re: Wien Bridge project
« Reply #130 on: April 25, 2021, 09:24:56 am »
The LM6171 does not have the high DC loop gain of the NE5532, but it is quite a bit faster. At more than a few 100 Hz the actual loop gain is set by the GBW and no longer the DC gain.

With the fast LM6171 using an extra buffer can be tricky with stability. So the high GBW also comes with a disadvantage.
The extra buffer is to reduce thermal effects, but also to reduce distortion from loading the output stage (e.g. output stage cross over).
 

Offline richlooker

  • Regular Contributor
  • *
  • Posts: 104
  • Country: no
Re: Wien Bridge project
« Reply #131 on: April 25, 2021, 01:25:47 pm »
OK, I'll settle with LM6171 for now, assuming that CMRR is not (yet) the main contributor to THD. As the LM6171 has a much lower output impedance / higher current drive capability than NE5532, I'm skipping the buffer for now. Thinking about it, I will use an LM6172, so I can swap it for an NE5532 and compare distortion figures directly. If the NE5532 chokes on the capacitive load, I will try buffering it's output with an LM6171.

Upon closer look, I see that the LM6172 CMRR is no worse than NE5532 - typ. 105db / min 70dB vs. typ. 100dB / min 70dB. The most important criteria for my application is that gain should fall off as little as possible 10Hz -> 100kHz; in that department the LM6172 wins. But testing will show :)

Linear Technology Application Note 43: Bridge Circuits, figure 45, seems to be a refinement of the circuit in the Jim Williams book; I'll start there:



"Figure 46 shows results. Distortion (Trace B) drops to 0.0018% and is composed of 2f, some gain loop rectification artifacts and noise. For reference the circuit’s output (Trace A) and the LT1055 output (Trace C) are shown."



With the S&H peak detector, I will have a ruler-flat trace C, so potentially the THD should be significantly lower.

With respect to JFET selection, I consulted Fairchild Application Note 6609: Selecting the Best JFET for Your Application:



2N5458 is listed as a prime choice for voltage variable resistor, it's forward transfer admittance is in the same ballpark as 2N4338, it's listed as symmetric (drain and source interchangeable), the range for Vgs(off) is a bit wider but that should be OK. I'll use this one.

With the negative feedback network resistor values as specified in figure 45, gain of 3 (assuming opamp open-loop gain = ∞) will be achieved when the parallel of 560Ω, 20k (assuming the 20k trimmer in middle position) and Rds equals 400Ω. This happens when Rds is ~1.5k, which should be a good operating point for 2N5458.

I would like the oscillator to have an adjustable RMS from 0dB/0.775V (for lowest distortion) to +12dB/3.1V - I will replace the LT1004 reference with a variable reference based on TL431C (or a simple voltage divider potentiometer, assuming the voltage supply is sufficiently accurate and stable)
« Last Edit: April 25, 2021, 02:19:58 pm by richlooker »
 

Offline RoGeorge

  • Super Contributor
  • ***
  • Posts: 3081
  • Country: ro
Re: Wien Bridge project
« Reply #132 on: April 25, 2021, 03:18:42 pm »
It has 18 ppm distortions instead of only 3 ppm.

Why is that considered a refinement?

Offline richlooker

  • Regular Contributor
  • *
  • Posts: 104
  • Country: no
Re: Wien Bridge project
« Reply #133 on: April 25, 2021, 05:19:32 pm »
It has 18 ppm distortions instead of only 3 ppm.

Why is that considered a refinement?

I want to see what I can achieve with a JFET, so I'm referring to this:



Not this:

« Last Edit: April 25, 2021, 05:21:34 pm by richlooker »
 

Offline richlooker

  • Regular Contributor
  • *
  • Posts: 104
  • Country: no
Re: Wien Bridge project
« Reply #134 on: April 25, 2021, 09:51:41 pm »
Does not work. It saturates. The circuit is incapable of driving gate to a sufficient negative voltage:



This is designed for 2N4338, which has a particularly high Vgs(off):



2N5458 is not compatible here:


« Last Edit: April 25, 2021, 09:53:58 pm by richlooker »
 

Offline richlooker

  • Regular Contributor
  • *
  • Posts: 104
  • Country: no
Re: Wien Bridge project
« Reply #135 on: April 26, 2021, 10:29:37 am »
Snippet from the datasheet for the LT1055, used as integrator/servo in Jim Williams' circuit:



Looking at this arrangement again, it's clear that it's severely limited in it's ability to drive the gate negative. With +/-15V supply, the LT1055 can (best case) swing to about -13.5V. Assuming the trimmer is in center position, the resistance between gate and ground is ~5k, which means -13.5V at A2 output gives -0.643V at gate. Maybe Williams just by chance used a 2N4338 with particularly low Vgs(off), towards the minimum specification, and did not deliberate around this, as he quickly moved on to the optocoupler.



Now consider the arrangement described in this article: https://sound-au.com/articles/sinewave.htm

"A FET used as a variable resistance, and these are convenient, cheap, and work well enough so long as the (AC) voltage across the FET is kept to a minimum.  Providing an AC signal at the gate which is exactly half the voltage on the drain helps dramatically, and even harmonics (2nd, 4th, 6th, etc.) are effectively cancelled, leaving only the small odd harmonic residuals.  C2 would normally be connected in series with R5, but that creates a second time constant.

To prevent this JFET 'feedback' from creating two time constants, one based around each capacitor - C1 and C2 (the latter shown in grey), it's better to direct-couple the JFET gate to C1, and use C2 in the drain circuit as shown (in series with the feedback circuit).  [C1 here is the integrating capacitor after a rectifying diode] C2 needs to be a relatively high value, such that there is little or no voltage across the cap at any frequency selected.  This means it will be an electrolytic because a value of at least 220µF is needed, based on 'typical' feedback resistance values and a minimum frequency of 10Hz.  Lower frequencies require a larger capacitor.  Doing it the way shown does add a small perturbation as the JFET's gate voltage changes, but as there's only a few microamps available through R4 and R5 it has a minimal effect on the output.

While there are countless JFET stabilised oscillator circuit to be found on the Net, almost none are wired properly.  Many don't include the drain to gate feedback at all (so distortion will be unacceptably high), and a few get tantalising close, but get the feedback path wrong.

Done properly, a JFET can provide distortion performance that is as good or better than a lamp or thermistor.  In simulations (real life will be worse), I've managed to achieve less than 0.001% THD, using both Wien bridge and state-variable topologies, but it's not known how well that will translate to reality.  Remember that the lower the voltage across the JFET, the lower the distortion can be"




This exploits the fact that the servo opamp output presents a low-impedance DC point, which for AC is equivalent to ground, making R4 and R5 a 1:2 voltage divider, achieving the exact same result as Williams' circuit, but without the extra gate-to-ground resistor.

The 560Ω resistor drain-source in Williams' circuit is already optimized to reduce the impact of the JFET, so the "distortion null" pot is not necessary.

With respect to C2, I don't understand what purpose it serves, as the feedback point it will connect to is ground-referenced, and simulation has shown no difference with/without, but I will try distortion measurements to see whether it makes any difference in practice.
« Last Edit: April 26, 2021, 12:48:58 pm by richlooker »
 

Offline bsfeechannel

  • Super Contributor
  • ***
  • Posts: 1258
  • Country: 00
Re: Wien Bridge project
« Reply #136 on: April 26, 2021, 09:43:49 pm »
With respect to C2, I don't understand what purpose it serves, as the feedback point it will connect to is ground-referenced, and simulation has shown no difference with/without, but I will try distortion measurements to see whether it makes any difference in practice.

1970's HP209A, 4Hz to 2MHz oscillator, from where Jim Williams may have drawn inspiration for the use of a JFET in the AGC loop, has a capacitor between the drain and the gate of Q8, probably to avoid messing with Q1's bias.

« Last Edit: April 26, 2021, 09:48:18 pm by bsfeechannel »
 
The following users thanked this post: richlooker

Offline Vovk_Z

  • Frequent Contributor
  • **
  • Posts: 652
  • Country: ua
Re: Wien Bridge project
« Reply #137 on: April 27, 2021, 02:41:10 am »
You may decrease 100k resistor to 47-51k, and you'll get -1.1VDC.
 

Online Kleinstein

  • Super Contributor
  • ***
  • Posts: 9216
  • Country: de
Re: Wien Bridge project
« Reply #138 on: April 27, 2021, 07:03:17 am »
....
With respect to C2, I don't understand what purpose it serves, as the feedback point it will connect to is ground-referenced, and simulation has shown no difference with/without, but I will try distortion measurements to see whether it makes any difference in practice.
AC coupling for the variable resistor JFET may be a good  idea if the amplifier in the oscillator has a significant offset, e.g. as shown in the HP circuit. With an OP amplifier for the osciallator there is susually very little DC offset and thus no real need for the large C2* on top of the FET.  C2 at the "alternative position" is  for a different reason. It may help with a FET that needs a relatively high negative bias for the operation point, so that one can still use a divider between the gain control OP and the FET and thus get away with a smaller cap at the OP.  With a 2N4338 one would likely not need C2, the 2N5458 may need it. The 2 positions for C2 and C2* are not fully equivalent.

C2 also effects stability of the control loop. Here it can be different between the simple peak detector with a diode and other amplitude measurement modes.
 

Offline richlooker

  • Regular Contributor
  • *
  • Posts: 104
  • Country: no
Re: Wien Bridge project
« Reply #139 on: April 27, 2021, 12:14:27 pm »
In simulation, a large C2 "on top of" the JFET makes no difference. C2 in series with the drain-gate resistor, on the other hand, turns out problematic, it leads to amplitude bounce/oscillation. Too small and the drain-gate feddback gets frequency-dependent, eg. not effective at lower frequencies. Too large and the amplitude takes forever to stabilize.

WIth respect to THD, I have been thinking about a new approach; I have seen that THD is something like exponentially proportional to oscillator RMS. What if I use the lowest-noise opamp I have - NJM2114L (forgot this earlier, as SIP-opamps live in their own drawer) - and tune the oscillator for -6dB/0.3875V RMS, and use the second opamp to amplify the signal 18dB/8x ?
 

Offline Vovk_Z

  • Frequent Contributor
  • **
  • Posts: 652
  • Country: ua
Re: Wien Bridge project
« Reply #140 on: April 27, 2021, 05:30:53 pm »
Do you mean a composite amplifier? If not, then it doesn't help. Still, you can try.
« Last Edit: April 27, 2021, 05:36:29 pm by Vovk_Z »
 

Offline Vovk_Z

  • Frequent Contributor
  • **
  • Posts: 652
  • Country: ua
Re: Wien Bridge project
« Reply #141 on: April 27, 2021, 05:39:29 pm »
I have seen that THD is something like exponentially proportional to oscillator RMS. What if I use the lowest-noise opamp I have - NJM2114L
If we'll look at your oscillator spectrum at your post « #111 on: April 21, 2021, 09:43:00 pm », then we see there that noise is not your problem. The main THD contributor is a non-linearity.
« Last Edit: April 27, 2021, 05:51:00 pm by Vovk_Z »
 

Offline richlooker

  • Regular Contributor
  • *
  • Posts: 104
  • Country: no
Re: Wien Bridge project
« Reply #142 on: April 27, 2021, 06:20:44 pm »
If we'll look at your oscillator spectrum at your post « #111 on: April 21, 2021, 09:43:00 pm », then we see there that noise is not your problem. The main THD contributor is a non-linearity.

Exactly. Non-linearity in the JFET voltage-controlled resistance. I saw as I reduced the oscillator amplitude that THD fell dramatically; when reducing the fundamental by 6dB, 2nd and 3rd harmonic dropped by 12dB. The reason I am thinking low noise opamp is that by reducing amplitude, the fundamental also gets closer to the noise floor, ie. S/N is reduced. And I need to amplify the signal to get the +12dBu output level I need.
 

Online Kleinstein

  • Super Contributor
  • ***
  • Posts: 9216
  • Country: de
Re: Wien Bridge project
« Reply #143 on: April 27, 2021, 06:56:02 pm »
One can reduce the voltage at the JFET with the parallel resistor. The downside is that this also reduces the adjustment range, so one needs the resitors / capacitors to set the frequency to be better tuned.

One the other side on could add adjustment range by switching in some resistors digitally, e.g. with relays or low R MOSFETs. This would add digital coarse trim, so one can get away with less analog trim via the JFET. With 2 digitally switched resistor one could reduce the needed range from the up to 4 times.

Having the resistor in parallel to the FET absorbes some of the variable part. So it maybe better to use more like a lower resistance fet (e.g. 2N4393 or the like).

It is not just the nonlinearity from the JFET, the amplifier can also contribute to distortion.
 

Offline richlooker

  • Regular Contributor
  • *
  • Posts: 104
  • Country: no
Re: Wien Bridge project
« Reply #144 on: April 27, 2021, 09:57:11 pm »
One can reduce the voltage at the JFET with the parallel resistor. The downside is that this also reduces the adjustment range, so one needs the resitors / capacitors to set the frequency to be better tuned.

The parallel resistor - P1 and R10 in this diagram - is selected to give the lowest possible voltage over the JFET while still allowing sufficient regulation range at all frequencies. If we assume Rds(on) is 100Ω;

Min gain, when Rds ~ ∞, is: 1 + (5.6k / (2.4k + 0.47k)) = 2.95
Max gain, when Rds ~ 100Ω, is: 1 + (5.6k / (2.4k + (470 * 100 / (470 + 100)))) = 3.25
Gain of 3 is when Rds in parallel with 470Ω equals 400Ω; this happens with Rds ~ 2.7k

The difference from Jim Williams' value of 560Ω for R5 is quite large; then gain of 3 happens with Rds = 1400Ω, which means twice as much current through the JFET.



One the other side on could add adjustment range by switching in some resistors digitally, e.g. with relays or low R MOSFETs. This would add digital coarse trim, so one can get away with less analog trim via the JFET. With 2 digitally switched resistor one could reduce the needed range from the up to 4 times.

I don't want to go down that route. If required, I could add a deck to the rotary switch for frequency range to switch resistors, but I hope the use of a sufficiently high GBW opamp the gain variance with frequency will be small.

Having the resistor in parallel to the FET absorbes some of the variable part. So it maybe better to use more like a lower resistance fet (e.g. 2N4393 or the like).

I doubt that; while the voltage over the JFET determines it's distortion, the current through it determines how much this contributes to the signal.

It is not just the nonlinearity from the JFET, the amplifier can also contribute to distortion.

I know. First I will see how I can reduce THD from the JFET; then, if I am not satisfied, I may explore opamp type and amplifier topology options.
 

Online Kleinstein

  • Super Contributor
  • ***
  • Posts: 9216
  • Country: de
Re: Wien Bridge project
« Reply #145 on: April 28, 2021, 06:52:13 am »
The variations in the required feedback setting with frequency are not so much the GBW of the OP. A main part are just tolerances of the capacitors / resistors to set the frequency. There is nothing magic about a gain of 3. Depending on the R and C in the frequency setting network, the required gain can be from some 2.7 to 3.3.  So one can trim the resistors to get a more uniform gain.

The relatively low value resistor in parallel to the JFET limits the adjustment range and may help to get a more uniform response for the amplitude control loop. However it requires a higher voltage at the FET to get the same trim range.

A lower resistance FET and less effect of the parallel resistance could help to operate the FET with less voltage across. The difficulty is that the control side gets less linear and thus the stability of the amplitude control loop gets slightly more difficult. One may have to adjust R4 slightly different and possibly limit the voltlage at the gate, not to turn the FET off too much.
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 17420
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: Wien Bridge project
« Reply #146 on: April 28, 2021, 08:09:28 am »
How much adjustment range are we looking at here?

My understanding of JFETs is, they're most linear for |Vds| < Vgs - Vp.  So, for a given peak amplitude |Vds|, higher Vp is desirable, and Rds should be varied from Rds(on) to maybe a few times higher, before the above limit is reached.  The important thing being, Rds is not, in general, adjustable all the way from Rds(on) to infinity, in a linear manner, for any given |Vds|.

(I don't think that's modified by the linearization (resistors from D to G to bias), but I would be interested to see evidence otherwise.)

We shouldn't need to hand-wave and empirically study this system; we need only know the range of resistance required, and this can be found by measuring the bias / control voltage while varying only a series resistor in the path (and not trying to reduce Vds or adjust resistance range with a series-shunt resistor divider before it).  By plotting Rs vs. operating conditions/settings (frequency and temperature I suppose?) we can determine the minimum and maximum required values.  Further, we can tweak ranges as needed to tighten up this spread.  Finally, we can design a JFET circuit to deliver the required adjustment range, and that should simply be it.  With the JFET operating in, whatever its most linear range is (if not Vgs ~ 0 then wherever -- this can also be measured independently by setting up a voltage divider with it).

I suspect series/shunt resistors are just a hack, as if you don't need that adjustable range in the first place, why use that JFET at all, or why not change all resistor values to simplify the circuit?  (Given that the feedback resistance can't drop too far due to op-amp capacity, nor rise too much due to capacitance and leakage.)

I haven't been following this thread in great detail so I may've missed this, but I don't recall this having been performed, or proposed, yet.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline richlooker

  • Regular Contributor
  • *
  • Posts: 104
  • Country: no
Re: Wien Bridge project
« Reply #147 on: April 28, 2021, 01:51:58 pm »
The variations in the required feedback setting with frequency are not so much the GBW of the OP. A main part are just tolerances of the capacitors / resistors to set the frequency. There is nothing magic about a gain of 3. Depending on the R and C in the frequency setting network, the required gain can be from some 2.7 to 3.3.  So one can trim the resistors to get a more uniform gain.

To my best knowledge, there _is_ something magic about a gain of 3, which is the gain that will sustain oscillation for a Wien bridge with perfect and perfectly matched timing components. The tolerances of the capacitors play a role, but this is easily controllable. I use only 1% components, and select matched pairs from a larger pool, to ensure they match to within 0.5%. BTW the required gain will never be below 3, except when the control loop needs to reduce amplitude the gain will be lowered until it stabilizes. And I have tested the amplifier without positive feedback across 10Hz-100kHz, and overall gain drops noticably (but not significantly) over the 10kHz-100kHz decade. This was measured with an LM6172; NE5532 or similar will drop off earlier.

The relatively low value resistor in parallel to the JFET limits the adjustment range and may help to get a more uniform response for the amplitude control loop. However it requires a higher voltage at the FET to get the same trim range.

The point is that the trim range need not be great; at 2.95 oscillation will stop, and at 3.25 there is just enough headroom so that oscillation can start and be sustained acros  the entire frequency range. I don't know why a low value parallel resistor should require a higher voltage range across the JFET.

A lower resistance FET and less effect of the parallel resistance could help to operate the FET with less voltage across. The difficulty is that the control side gets less linear and thus the stability of the amplitude control loop gets slightly more difficult. One may have to adjust R4 slightly different and possibly limit the voltlage at the gate, not to turn the FET off too much.

The key is really that you need to balance three interdependent concerns;
  • Ensure sufficient (but not more than sufficient) control range
  • Minimize JFET Vds
  • Operate the particular JFET within it's linear range

And then further minimize the impact of channel length modulation through drain-gate feedback.
 

Offline richlooker

  • Regular Contributor
  • *
  • Posts: 104
  • Country: no
Re: Wien Bridge project
« Reply #148 on: April 28, 2021, 02:00:47 pm »
How much adjustment range are we looking at here?

My understanding of JFETs is, they're most linear for |Vds| < Vgs - Vp.  So, for a given peak amplitude |Vds|, higher Vp is desirable, and Rds should be varied from Rds(on) to maybe a few times higher, before the above limit is reached.  The important thing being, Rds is not, in general, adjustable all the way from Rds(on) to infinity, in a linear manner, for any given |Vds|.

(I don't think that's modified by the linearization (resistors from D to G to bias), but I would be interested to see evidence otherwise.)

We shouldn't need to hand-wave and empirically study this system; we need only know the range of resistance required, and this can be found by measuring the bias / control voltage while varying only a series resistor in the path (and not trying to reduce Vds or adjust resistance range with a series-shunt resistor divider before it).  By plotting Rs vs. operating conditions/settings (frequency and temperature I suppose?) we can determine the minimum and maximum required values.  Further, we can tweak ranges as needed to tighten up this spread.  Finally, we can design a JFET circuit to deliver the required adjustment range, and that should simply be it.  With the JFET operating in, whatever its most linear range is (if not Vgs ~ 0 then wherever -- this can also be measured independently by setting up a voltage divider with it).

I suspect series/shunt resistors are just a hack, as if you don't need that adjustable range in the first place, why use that JFET at all, or why not change all resistor values to simplify the circuit?  (Given that the feedback resistance can't drop too far due to op-amp capacity, nor rise too much due to capacitance and leakage.)

I haven't been following this thread in great detail so I may've missed this, but I don't recall this having been performed, or proposed, yet.

Tim

The problem I am trying to solve here is not to get a fast and stable AGC feedback loop; this is already understood and achieved. The challenge is how to minimize the harmonic distortion from JFET channel-length modulation. The most important concern is not whether the JFET is operating within the linear range (this is most important for the control loop) but that Vds is as low as possible.

The required gain adjustment range is approx 2.95-3.25. The JFET - or some other AGC mechanism - is an absolute requirement; the oscillator cannot stabilize without it. You are welcome to try stabilizing a Wien bridge by tweaking resistors, but don't hold your breath while waiting for it to become stable :)

JFET drain-source current equations, from https://www.multisim.com/help/components/jfets/jfet-model/

For the linear region, if Vds = 2*Vgs, the equation becomes:

 -2*β*Vto (1 + λ*Vds)

- and Ids gets a linear relationship to Vds (ie. ohmic) as opposed to exponential; this is why feeding 50% of Vds back to gate is crucial.


« Last Edit: April 28, 2021, 02:13:51 pm by richlooker »
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 17420
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: Wien Bridge project
« Reply #149 on: April 28, 2021, 03:42:35 pm »
Well yeah, I already know AGC is required, that's the point...

So 2.95-3.25?  Why not 3.05?

Is the difference the aforementioned drop in loop gain at the high end?

Why not tweak out a frequency-dependent gain error using an RC network?  (This will introduce phase shift -- indeed, complementary to the op-amp's own phase shift, which is part of the effect as well!)

Note that that formula works for the SPICE component.  But real devices aren't piecewise functions, they fade smoothly between regimes.  How should we express this fact?  And do we know whether it's responsible for the dominant part of distortion under whichever conditions?

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf