I managed to build the demo FPGA-A200T-3 project included in the NiteFury git repo. Took a bit tinkering with latest vivado. Loaded it on the CLE-215+, and it's recognized by the driver. It even passes XDMA tests, sometimes. About every 6th test returns bad data. It's usually in the 18th bit, which gets flipped.
I suspect the clocking of memory is at fault. Initially project sets the clock at 1850ps, which is outside the range that the IP wizard dialog wants.
I have tried 3077ps (So I can get exactly 200Mhz input) and it does much better as far as error rate, but still not perfect. With that setting I get about 1 in 20 tests fail, same failure mode.
Anyone managed to get the XDMA tests to reliably pass? Would you kindly share the parameters for the mig_7series core you made to run?