I don't know, but for the ASIC on the company where I work (much more complex than the batteriser chip, and made from an FPGA) it seems that the reasonable minimum was about 1K to 10k chip, but it was comparing to a FPGA solution, so it's strictly depends on the product and the price you agree to put on the chip. (The product we made is not cheap)
I would says that 10K is the "standard" minimum, mais I may be wrong, there are maybe people there that knows more than me on this point
Oh and for the three step, the chip took at least 2 years between the FPGA to the ASIC, and the ASIC had multiple revision (at least 4 or 5) and there are still bugs found and more to be found, the QA was a bit poor TBH on that project, that explain why it was so slow, and there is no real expert in this company on making ASIC, nor FPGA programming, yeah, at some point they wanted to put everything, even the CPU in the FPGA, without good knowledge in the company for that, as for the fact that we use Linux with no one that had experience on it, that was before I joined..., at least 2 years after the project started, yeah that's crazy.
Anyway, the ASIC made by my company is much more complex than the bateroo one, but you can't do anything on the first time perfect, you'll need a lot of test and trial, there are a lots of reason for failure, not necessarily because of your design..
I would recommend to read the Parallax Inc. forum, especially about the propeller, Chip Gracey give a lot of information about the design of his chip the Propeller (yes he made it all by himself, and mostly by hand) about all the problem they had during the first batch and testing of the chip, it's quite interesting.
And for my three months, that's a rough estimation, I seriously doubt that any company was able to make a chip in a three month time span, even small changes will takes a lot of test, either from the manufacturing point of view, and from the usage point of view. A single change could easily break the whole chip... See it as PCB design 100 to 1000x more complex (or even more)
And it's especially true when you want to have the level of performance they claim.
It's for purely the digital domain, but look at all the compilation options you have for "simple" FPGA design, plus all the optimisation that can be done (and need to be done) if you want more than what the automatic optimiser will do...
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