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Hi,
a common way to protect an IC is to clamp the inputs between Vdd/Vcc and Vss/GND with chottky diodes.
Protecting an ADC input can easily be done like that, but I came across two different variants of this simple circuit and I'm wondering in which cases one would prefer variant A over B or vice versa.
From my naive point of via, variant B seems "dangerous" as the diodes would receveive the full current in an over voltage event and might be destroyed. Variant A in constrast would limit the maximum current with R1 and R2. I can only imagine that R1/R2 with D3/D4 form a voltage divider because of the reverse leakage of the diodes and this might influence the input signal's reading, but that's just a hypothetsis of mine. I did not find any explanation in which situation one would prefer a specific variant.
Thanks for any light shed!
Regards,
Kryp
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It depends on the signal source: in the variant B the signal source has to somehow limit the current. Often one also considers a combination of both: so resistors before and after the clamping diodes. The resistors after the clamping diodes can often be smaller (e.g. 100 Ohms - 1 K) and still limit the current to a safe level for the ADC. This is especially needed if the diodes are not Schottky types (e.g. due to leakage) or with releagive large current spikes so that even the Schottky diode get quite some voltage drop.
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Afaik all chips today have such a protection built in (on each pin). The diodes inside can survive say 5mA happily, so what one usually need is to limit the current with a resistor (at the input pin)..
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Input of your ADC:
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@kleinstein, thanks for the clarification on when to use what variant and for pointing out that's not a "this or that" question.
@imo: Lazy me...thanks for the excerpt from the data sheet. Actually, I'm using the MCP3208 but it's data sheet shows the esxact same input design. That means, in my case, I can get rid of the external diodes and just limit the current.
Regards,
Kryp -
When using the chip internal diodes for protection, keep in mind that with many chips these are not normal diodes, but in some situations inject current to the substrate and this way can effect other parts of the chip, like other channels of a mutiply input ADC. So it can still make sense to have external diodes or a similar solution so that other channels are still OK if one is overrange.
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If you look at fig 4 in the datasheet you can see how the choice of current limiting resistors affect the frequency response of the ADC. Something like 1k with no diodes is probably enough, you only need to limit the internal ESD diodes inside the ADC. In variant b, the diodes will be damaged if there is no current limit from the signal source. Read section 4.1 Something like 1k with no external diodes is probably enough, you only need to limit the internal ESD diodes inside the ADC. As pointed out it depends on the external environment the input signal comes from.
You can use usb line protectors, they have very low capacitance.
Finally you can use a hybrid of your variants. Use an input resistor of 100R to limit the fault current in the diodes and a second low value resistor (say 100R) from the diodes to the ADC. This gives you the best of both worlds and lets you use low values.
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be careful when adding series resistors on ADC inputs. Many ADC have an internal sample and hold. the sampling time is short and they store the sample on a capacitor. if you add series resistance you are creating an RC filter and your ADC may measure wrong !
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Thanks for the follow up!
In the meantime, I read the complete data sheet and I came across the internal sample and hold feature.
As the internal resistor is 1k and the precision of my input readings are not critical I think adding 200 ohms for protection to the ADC's input is okay.
Basically, I just need reasonably precise ratiometric readings of some hall effect joysticks and photo-electric distance sensors. Any constant (known) error can be calibrated out in software.
Attached you'll find what I did based on the responses I got. Thanks!
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There is an issue- 100R-200R may be too low, I wouldn't use that circuit. In the case where the ADC (MCU) power is off yet the analog input has voltage present, it can actually power up your MCU, or overvoltage it. If say +12V came in to an analog channel, it can kick the +5V rail up through the resistor. Or cause a reset problem if there is power coming in from an analog sensor and with MCU power off, the MCU rail does not not fall low enough to properly stop/reset the MCU.
It really depends on how many power sources are present in your project and if the sensors are powered from another system, compared to the MCU portion. If you want coverage for those kind of faults, then a zener is used.
Analog input protection is unique for each part. Many newer microcontrollers don't always have input diodes. I was surprised for example:
STM32 AN8499 "The parasitic diode in the analog domain is connected to VDDA and cannot be used as a protection diode".
"Positive-injection current is the current induced when VIN > VDD. For STM32 devices, the maximum positive-injection current on TT and FT GPIO is defined as N/A or 0 mA." -
Analog input protection is unique for each part. Many newer microcontrollers don't always have input diodes. I was surprised for example:
All CMOS devices have these diodes and they should NEVER be used as protection UNLESS it is clearly stated you can. do not assume they are there for protection against external events. They are there for ESD events during manufacturing/handling. Not during runtime
This is a common misconception -
On the Internet, these (substrate) diodes are getting taken for granted, protecting with the assumption they're good for higher currents, not always specified on the datasheet.
Automotive parts have the diodes rated for significant injection current, it's the norm for them in order to keep costs/parts count low. Example: 'hc4851 or 'hct4067 etc.
A bit confusing some IC specs are for 0.3V others like OP 0.6V for those internal diodes.
If OP is expecting protection with say a sustained 12V or 24V input, it's not looking good IMHO. -
Another consideration when external protection diodes are used, especially schottky diodes, is that it is very easy for their leakage current combined with the source resistance, including any series protection resistance, to compromise the accuracy of the converter. One solution for this is to bootstrap the diodes so that they always have zero volts across them, but this may be inadequate in higher precision applications unless low leakage diodes are used.
Another solution is to use an operational amplifier to drive the ADC which will automatically limit the drive to the operational amplifier's output range. Of course now the operational amplifier needs to be protected but this can be much easier.
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One of the effects in putting protection resistors in front of a sampling ADC is that the error becomes proportional to the difference between the previously sampled channel and the latest selected channel.
One way to overcome this is to create an RC combination at the input, and this works well for sensors that only need a slow sampling speed. A combination of for example 100kOhm and 100nF will both add some protection with the 100k resistor, and the 100nF capacitor completely swamps the small sampling capacitor. It also significantly attenuates high frequency disturbances.
An easy and fun experiment you can do at home is to directly connect a (for example 1uF) film capacitor directly to the ADC of a uC, sample it repeatedly and output the value to a display or serial port. The value only changes very slowly, because the charge on the sample capacitor hardly changes.
However, if you connect one of the other pins of the mux to GND and yet another to Vcc and then sample alternatively between one of those and the capacitor, then you can either inject or extract charge from the film capacitor, and this change is quite significant. If you only sample the capacitor, it may slowly (order of minutes) drift to about half the supply voltage, while when you sample (at a few kHz) between another voltage and the capacitor, you may either charge or discharge the capacitor a lot quiker (handful of seconds). -
One of the effects in putting protection resistors in front of a sampling ADC is that the error becomes proportional to the difference between the previously sampled channel and the latest selected channel.
A simple way to avert this type of behavior is to always sample zero first, then the actual intended sample. This effectively isolates the previous intended input sample from the next intended input sample. Of course this doubles the ADC sample rate.
Best, -
One of the effects in putting protection resistors in front of a sampling ADC is that the error becomes proportional to the difference between the previously sampled channel and the latest selected channel.
A simple way to avert this type of behavior is to always sample zero first, then the actual intended sample. This effectively isolates the previous intended input sample from the next intended input sample. Of course this doubles the ADC sample rate.
Best,
In some weird corner cases you have to resort to such trickery; example being STM32 hardware designers being such degenerates that they forgot to add buffer (transistor cost: $0.00000000000001) or a capacitor (much more expensive, of course) on the internal temperature sensor, so there is no way to sample it in any application requiring continuous sampling of something else at any meaningful rate.
But usually, the right thing to do is to just satisfy the ADC input impedance requirement, either by:
1) opamp buffer for high BW, or,
2) for low BW such as temperature sensors or battery voltage sensing, capacitor significantly larger than Csample (typically 100nF BOM reuse, but for high-accuracy 16-bit ADC might even need up to 1uF. Do the math.)
2) always solves sampling time problem (allows using of shortest sampling time), but still imposes a (more relaxed, but not non-existent) impedance requirement for whatever is feeding the capacitor, as a function of sample rate of that particular input. If you sample too often, even that large capacitor starts drifting in voltage due to charge injection from/to sampling capacitor. But now it is enough that source impedance is low enough to supply Csampl equivalent charge during every sample period, which is much easier to satisfy than having to deliver the same charge in sampling time, a much much shorter time. For example, you only need to read battery voltage every second. So sample period for that channel is 1 second (and only this is significant; other channels can happily sample at 1 MSPS). But sampling time can be just tens of ns for a fast SAR ADC, and sometimes it is not configurable, or if it is, you can't waste time sampling a slow channel because you have other channels to serve. In such cases the $0.001 100nF capacitor does the trick fine. -
Hey,
thanks! Wow, to be honest, I'm overwhelmed by all these responses.
I know, I asked a somewhat generic question and there is obviously only one correct answer and it seems to be "it depends".
To clarify my setup: I'll provide Vref and GND to the sensors in questions. Vref is generated locally with a 5V LDO regulator. Nothing else "should" be connected to the ADC. As I only care for precise ratiometric readings, this seems reasonable to me.
Inside my application, I use encoded plugs which are only used for these sensors. So besides static discharges and EMI I do not "expect" any other harmful input signals.
I like the propsal from Doctorandus_P. In fact, my sampling speed is secondary in my application and using a RC combination sounds good.
As this only takes two tiny components per channel, I would change my curcuit like that (see attachment).
@Doctorandus_P: You proposed R = 100k and C 0.1u. As R has a "double" role: limiting the fault current and setting the time constant, I think, I can get away with 10k in my applicatio. What do you think?
@Siwastaja: Internal sampling RC of the ADC used is 1k and 10pF. So 100nF is larger by a factor of 10³. That's fine!
Regards,
Kryp
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Analog input protection is unique for each part. Many newer microcontrollers don't always have input diodes. I was surprised for example:
All CMOS devices have these diodes and they should NEVER be used as protection UNLESS it is clearly stated you can. do not assume they are there for protection against external events. They are there for ESD events during manufacturing/handling. Not during runtime
This is a common misconception
CMOS ESD protection usually isn't a simple diode anymore but a more complex "circuit", this is especially true for modern fast CMOS where the I/O pad capacitance is minimized.
In all the chips we've designed the CMOS foundry provided a variation of ESD protection circuits that were carefully designed and tested to verify performance, and many were tailored for outputs vs inputs and even for VDD and VSS power supply pads. Some of these circuit had a non-monotonic or holdback behavior under heavy clamping currents.
Here's a few sources that touch on the subject of CMOS ESD protection and show the actual IC structures involved.
https://www.intechopen.com/chapters/66524
https://ieeexplore.ieee.org/document/7870016
https://ieeexplore.ieee.org/document/966442
And an old TI paper that illustrates the effects of ESD induced CMOS Latchup which we encountered long ago with the loss of a couple very expensive Analog Devices hybrid DACs where Latchup was induced by improper power supply sequencing at the microsecond level during mains power on!!
https://www.ti.com/lit/an/slya014a/slya014a.pdf
Best,
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In some weird corner cases you have to resort to such trickery; example being STM32 hardware designers being such degenerates that they forgot to add buffer (transistor cost: $0.00000000000001) or a capacitor (much more expensive, of course) on the internal temperature sensor, so there is no way to sample it in any application requiring continuous sampling of something else at any meaningful rate.
But usually, the right thing to do is to just satisfy the ADC input impedance requirement, either by:
1) opamp buffer for high BW, or,
2) for low BW such as temperature sensors or battery voltage sensing, capacitor significantly larger than Csample (typically 100nF BOM reuse, but for high-accuracy 16-bit ADC might even need up to 1uF. Do the math.)
2) always solves sampling time problem (allows using of shortest sampling time), but still imposes a (more relaxed, but not non-existent) impedance requirement for whatever is feeding the capacitor, as a function of sample rate of that particular input. If you sample too often, even that large capacitor starts drifting in voltage due to charge injection from/to sampling capacitor. But now it is enough that source impedance is low enough to supply Csampl equivalent charge during every sample period, which is much easier to satisfy than having to deliver the same charge in sampling time, a much much shorter time. For example, you only need to read battery voltage every second. So sample period for that channel is 1 second (and only this is significant; other channels can happily sample at 1 MSPS). But sampling time can be just tens of ns for a fast SAR ADC, and sometimes it is not configurable, or if it is, you can't waste time sampling a slow channel because you have other channels to serve. In such cases the $0.001 100nF capacitor does the trick fine.
One of the concerns with ADC or Sampler charge injection (either + or -) during sampling is the effect this has on the driving amplifier. This was discovered eons ago with the high speed ADCs wreaking havoc of the signal source amplifiers and inducing significant ringing in those amplifiers. These effects caused the development of special purpose high speed op-amps designed specifically to drive such ADCs and they had very low dynamic output impedances (either open or closed loop) under high speed transient conditions. These were not trivial designs and maybe why they were not incorporated into the front end of some integrated ADCs within a more complex chip.
Should add, that the effect of charge injection resonates with the driving source op-amp which exhibits an inductive output behavior (rising output Z with frequency) under closed loop conditions, thus the induced ringing. This effect is even encountered with very high speed emitter followers where the emitter output becomes inductive and even can exhibit a negative real impedance due to the excessive phase shift from base to emitter when "looking" back at the emitter. We encountered this very behavior in our early works with advanced Silicon Germanium BiCMOS processes (IBM 7,8 and 9HP) a few decades ago.
Best -
In some weird corner cases you have to resort to such trickery; example being STM32 hardware designers being such degenerates that they forgot to add buffer (transistor cost: $0.00000000000001) or a capacitor (much more expensive, of course) on the internal temperature sensor, so there is no way to sample it in any application requiring continuous sampling of something else at any meaningful rate.
But usually, the right thing to do is to just satisfy the ADC input impedance requirement, either by:
1) opamp buffer for high BW, or,
2) for low BW such as temperature sensors or battery voltage sensing, capacitor significantly larger than Csample (typically 100nF BOM reuse, but for high-accuracy 16-bit ADC might even need up to 1uF. Do the math.)
2) always solves sampling time problem (allows using of shortest sampling time), but still imposes a (more relaxed, but not non-existent) impedance requirement for whatever is feeding the capacitor, as a function of sample rate of that particular input. If you sample too often, even that large capacitor starts drifting in voltage due to charge injection from/to sampling capacitor. But now it is enough that source impedance is low enough to supply Csampl equivalent charge during every sample period, which is much easier to satisfy than having to deliver the same charge in sampling time, a much much shorter time. For example, you only need to read battery voltage every second. So sample period for that channel is 1 second (and only this is significant; other channels can happily sample at 1 MSPS). But sampling time can be just tens of ns for a fast SAR ADC, and sometimes it is not configurable, or if it is, you can't waste time sampling a slow channel because you have other channels to serve. In such cases the $0.001 100nF capacitor does the trick fine.
One of the concerns with ADC or Sampler charge injection (either + or -) during sampling is the effect this has on the driving amplifier. This was discovered eons ago with the high speed ADCs wreaking havoc of the signal source amplifiers and inducing significant ringing in those amplifiers. These effects caused the development of special purpose high speed op-amps designed specifically to drive such ADCs and they had very low dynamic output impedances (either open or closed loop) under high speed transient conditions. These were not trivial designs and maybe why they were not incorporated into the front end of some integrated ADCs within a more complex chip.
Best
Yeah, and often ADC appnotes show a combination of the 1 and 2 (as enumerated by me above), and add a tad of RC filtering, too. Adding RC after the opamp fights against the whole idea of getting high BW, so it's always a careful compromise.
In any case, it's a wrong idea to think about adding Rs and Cs before ADCs as simple "RC filters". Sampling ADC is a bitch of a load. RC is not only used as simple 1st order analog filter, that is often just a side effect, but instead C is used to provide low impedance for the ADC, and R is used to protect, isolate, increase stability, etc. -
In any case, it's a wrong idea to think about adding Rs and Cs before ADCs as simple "RC filters". Sampling ADC is a bitch of a load. RC is not only used as simple 1st order analog filter, that is often just a side effect, but instead C is used to provide low impedance for the ADC, and R is used to protect, isolate, increase stability, etc.
Sampling ADC is a bitch of a load
Oh so true!!
This very charge injection effect was actually used in our early simulations to study the effects of instability in various circuits. We called it the "Pinging Source" where a SPICE PWL current source was configured as a Dirac Doublet (+ and - very narrow triangular current pulse with zero average area) was injected into a circuit and the response observed. The time domain response to the Doublet would revel the stability nature of the circuit under investigation, very powerful and simple simulation technique that proved extremely useful in our complex chip design.
Best