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I need to calculate trace width and pair spacing for a controlled-impedance differential pair running on a flexible printed circuit (FPC). I'm using Saturn PCB Toolkit's calculator, but I have doubts over which layer structure I should choose for FPC: 'edge-coupled external' or 'edge-coupled embedded'.
I'm leaning towards thinking that edge-coupled embedded is the correct option to use, because with FPC you have the core polyimide, top and bottom copper layers (with one being the diff pair traces, and the other ground plane), and then top and bottom coverlay. So because there is a polyimide layer on both side of the diff pair traces, that counts as embedded, right?
My other doubt is also concerning the coverlay layer thickness. My PCB manufacturer specifies 0.025 mm core thickness, 0.012 mm copper thickness, and 0.0125 mm coverlay thickness. So this makes a conductor height (H2) figure of 0.0375 mm. But the manufacturer also specifies the adhesive for the coverlay is 0.015 mm thickness. Should I take this into account too?
BTW, I wish Saturn PCB Toolkit would give you the option to enter a custom copper thickness. I need to calculate based on 12µm, but it only has options for 9 and 18. I've figured that I should probably take the average of results for both. Similar with the dielectric constant (Er), because the specified figure for the core polyimide is different to the coverlay: 3.3 vs 2.9, so I'm thinking calculating with something in the middle will suffice, like 3.1.
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I'd treat it as embedded. Also when you say 12um copper is that because your supplier has specified 12um or because they have spec'd 3/8oz, which is theoretically 12um? You can bet that copper specified by weight will be at IPC minimum (from IPC-6012), which for 3/8oz is in fact only 9.3um.
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They specify 1/3 oz copper, which I believe is 12 um - unless that's wrong?
Anyway, I'm struggling to get a sensible trace width. I don't see how it's possible to do something in the range of 80-100 ohms diff impedance on FPC.
The PCB manufacturer specifies a minimum trace width of 3 mils, and absolute minimum of 2 mils - i.e. under 3 they don't guarantee it'll come out right. I can't get in that range of impedance without dropping below 3 mils.
And I'm seeing conflicting advice about ground fill. Never use solid planes on FPC, use cross-hatched; oh, but also you must have a solid reference plane for high-speed diff pairs... -
They specify 1/3 oz copper, which I believe is 12 um - unless that's wrong?
After working it out, I think that's right.
Mass = density × area × thickness, so thickness = mass ÷ area ÷ density. Density of copper is 8.935 g/cm3. PCB copper weight in oz is per square foot, so area of 1 ft2 = 929.0304 cm2. Mass of 0.333 oz = 9.44 g. So copper thickness = 9.44 ÷ 929.0304 ÷ 8.935 = 0.00114 cm = 11.4 µm. So they're actually rounding up. Or maybe it's actually 12 and they're rounding to a third when converting to oz.
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It seems you're on the right track with your approach to treating the differential pair as 'edge-coupled embedded'. The presence of polyimide layers on both sides of the trace pairs and the use of coverlay indeed suggests an embedded structure.
As for the coverlay thickness, it's typically included in the overall stack-up calculations because it contributes to the dielectric properties and the overall impedance of the trace. The adhesive layer's thickness, while thinner, could also be considered part of the overall dielectric, but its impact might be relatively minor compared to the coverlay and core materials.
Regarding the copper thickness, the conversion from ounces to micrometers can indeed be a point of confusion. The standard 1/3 oz copper typically corresponds to approximately 12 µm, but as you've calculated, it can be slightly less. It's important to use the most accurate value provided by your manufacturer or to measure it directly if possible.
For the dielectric constant (Er), using an average value when there's a discrepancy between the core and coverlay materials is a practical approach. However, it's worth noting that the Er value can significantly affect impedance calculations, so it's best to get as close to the actual value as possible.
Finally, achieving a specific impedance value on an FPC（e.g. [spam link removed]） can be challenging due to the limitations on trace width and spacing. The manufacturer's minimum trace width specifications must be respected to ensure quality and reliability. If the required impedance cannot be achieved within these limits, it may be necessary to reconsider the design or discuss alternative manufacturing options with your PCB supplier. -
Hmm... is that... ChatGPT I smell?
Yeah, thanks for copying and pasting some AI-generated stuff just to shill your company's services.
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I have designed a few custom FPC cables during my career. The 100 Ohm Diff pair impedance requirement is a bit difficult to implement in a 2-layer structure.
A few things in general:- Usually the insulation between the layers is 25µm - 50µm thick. It forces to make the conductors narrow. However, the connector pattern is larger than the conductor width. This causes a point of discontinuity i.e. return loss.
- If you want to fold or bend the FPC, it would make sense to use the Hatch pattern instead of the solid reference plane. The opening naturally increases the impedance, and incorrectly designed with fast edges causes a skew effect. You should read Barry Olney's (Managing Director of iCD) technical articles on the subject. Remember that he has opened FPC design as well.
- If it is a commercial product for which UL is required, the FPC manufacturer's structure should be used to avoid UL hassle.
Many commercially available High speed data FFC cables are one layer solutions. And yes, a differential pair(s) can be implemented that way too. Of course, taking into account the operating environment. -
Remove the ground plane and use side-by-side traces for higher impedance perhaps?
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I found Sierra Circuits have an online impedance calculator that specifically covers FPC under 'coated microstrip differential pair'. This is also what they describe FPC as in terms of impedance calculations in their blog articles.
The calculator allows you to enter different Er values for core and coverlay. If I plug in the appropriate values, and aim for an Zdiff of 85 ohms and a fairly sensible trace spacing of 0.2 mm, then it gives me a trace width of 60 um (~2.3 mils) to get actual Zdiff of 84.7 ohms. This is about what I managed to work out with Saturn PCB Toolkit using edge-coupled embedded calculations and fudging for a number between what was output for 9 and 18 um copper (62 um / 2.45 mils).
Things get much more sensible if I specify 50 um core polyimide thickness (gives trace width of 126 um / 5 mils), but I won't have that option - none of the cheaper players like JLCPCB or PCBWay offer anything other than 25 um core thickness.
If I aim lower, say 80 ohms, I can get 66 um trace width, which is more reasonable, but still < 3 mils. However, I note that in one of Sierra's articles discussing hatched ground planes, it says:QuoteSince the impedance of a trace across the hatch ground zone is greater than that of the solid ground region, the inductance of the trace must be reduced to keep the impedance under control. This is the reason why a trace should be built a little wider. This lowers the inductance of the trace and raises the overall capacitance with respect to the hatch ground.
(BTW, why the #$%& do they disable right-click and copy-paste on their website?! I had to break out the browser dev tools to copy it.
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So, if I use a hatched ground plane, I should be making my traces wider anyway. But I'm not sure by how much. Maybe if I have cross-hatched ground plane pattern that reduces the area of copper to around 60% (is there a way to calculate this from hatch line width and spacing?) I could increase my trace width by, say, 30%?