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I've been looking to try to practice building some small PSU circuits which are better than a 7805, and which would be able to filter out some of the HF noise which comes from cheap general purpose power-brick style DC supplies.
As it happens my cheap bench supply (eventek) seems to be quite a poor performer in this regard with dramatic ~30 MHz noise spikes. However, not being particularly familiar with RF, I was surprised at how difficult this appears to be to filter. However, I noticed that an unconnected probe picks up similar levels of noise, so I wonder if some of what I am seeing may be an issue with measurement, or radiated EMI.
As part of some earlier experiments, I built a small LDO module with integrated pi filter, and while this reduces the size of the measured spikes, it is nowhere near the attenuation I was expecting (because of some other route of conduction?). LT spice suggested ~100 dB, although I am aware that that may not be realistic.
Noise amplitude (V p-p) for various measurement points is as follows:
Lab PSU output terminals: 930 mV
LDO board input terminals: 150 mV
LDO board pi filter output: 23 mV
LDO board output terminals: 20 mV
Probe lying on bench unconnected: 22 mV
I've attached some measurements of the noise and figures illustrating the setup
Fig 1 - Noise measured at output terminals of PSU
Fig 2 - Physical setup
Fig 3 - Measurement probing technique
Fig 4 - LDO schematic
Fig 5 - LDO layout
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As it happens, I just finished a project that uses three closely related regulator models (the LT3045-1 positive 500mA and the LT3093 200mA negative) and I sweated over the PCB design. (Ultimately, I closely followed the demo board layouts.)
It looks like you've followed the NPN follower design from p.27 of the datasheet, and I'll be honest that I'm not entirely sure how some of the subsequent points are best handled in that configuration.
The only things that really stand out to me are the connections to R4 (Rset), C5 (Cset, i.e. Rset's stabilization cap), and their connection to the output caps C14 (NPN follower output cap) and C16 (LT3042 OUT cap).
I see that you followed the datasheet's instruction to Kelvin connect to the load ground, but I'm not so sure that's what they had in mind. If you look elsewhere in the datasheet, and on the (single-chip) demo board layout, they've a) placed the output cap REALLY close to the IC (a second, optional cap is shown in the demo board right by the output jacks at the edge of the board), and b) it uses a Kelvin connection to both ends of the output cap. Since you want the feedback loop to be physically as small as possible (so you don't have error currents flowing over longer distances), I'd think you'd want to have both C14 and C16 really close to the IC, and with their grounds as close as possible to each other, on the output side. Your layout creates a very long route for the Rset resistor's ground, but above all, has separated its stabilization cap from that same route. So rather than stabilizing, I think you've created two different routes for the high-frequency noise and the set current.
I'd see what happens if you desolder R4 and then solder it on top of C16, directly in parallel.
Go back and re-read the datasheet and the user guides and PCB layouts to the two demo boards. You'll notice that the multi-chip demo board doesn't use all of the techniques described in the datasheet (whereas the single-chip demo board uses most of them). Studying them closely will give you an idea of how they lay them out for top performance. The datasheet warns about ESR and ESL outside the feedback loop reducing performance.
One design approach your board definitely doesn't follow is to keep the input traces exactly the same (on different layers) to reduce magnetic coupling of noise. Study the single-chip demo board in particular to see how they did that.
Finally, I have no idea how much noise the NPN follower adds. I assume it's not zero, but I couldn't begin to guess how big an effect it has. -
TS should consider a common mode noise.
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Hi. Thanks for the comments.
I take the points about the layout. I accept I was being a little bit creative in my interpretation, and I perhaps chose a somewhat inappropriate project for my 2nd ever PCB.
I'll confess I struggled to understand what was going on in the single regulator demo board (although having revisited it, I suspect I was being confused by the lack of labelling of the traces to the measurement ports). So, I took a bit of a gamble leaving out the magnetic field cancellation, and also as it had been left out of a number of boards I'd seen for sale (not necessarily a good sign, I concede), and a successful board design posted elsewhere on this forum. (https://www.eevblog.com/forum/chat/why-did-my-lt3042-die/). Instead, I added some electrolytic caps to avoid the ceramic cap resonance problem.
In terms of the external NPN transistor, this has almost no effect on noise whatsoever. Both LT claim this in a technical note (https://www.analog.com/en/technical-articles/increasing-output-current-of-the-ultralow-noise-ultrahigh-psrr-lt3042-200ma-linear-regulator.html) and measurements on the other thread report this. There is an impact on PSRR, but I wasn't really aiming for that.
After some experiments, I think the problem is as Vovk_Z says: common mode noise compromising the measurements.
I made whatever changes I could to the board (rearranged the Kelvin connnections to R4/C5 and C14), added an ceramic cap to the twisted input wires (as a crude magnetic-field cancelled decoupler) but these did nothing measurable.
Then by accident I shorted the probe (tip and ground) to a ground pad on the board, and was surprised to still see the spikes unchanged on the scope. At this point, it became clear that this had to be a common mode problem.
I also tested the regulator with a battery, and when completely isolated, the regulator gave a clean output. However, if one side of the battery was connected to one side of the bench supply, the spikes came back at identical amplitude.
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There you go, then!
!
Yes, I’d say this was a fairly ambitious thing to do as your second PCB. (And I know precisely what you mean about working out how the demo board works. I had to analyze it carefully to figure out what they were doing.) But what’s also clear is that the IC will work fine with unoptimized layouts, you just won’t reach its maximum performance. -
AC (or any other high voltage level) powered AC/DC power suplies are well-known for high level of a common mode noise created.
Every time we work with AC/DC power supply we shold consider common mode filters.
I use ferrite clips a lot nowadays. I put them everywhere, on every instrument wire, even on oscilloscope probes.