This is either one of those simple things that just is not clicking, or I have it completely wrong. I have seen plenty of examples using an LED, nothing in a real circuit. If I am understanding right, these two circuits should be equivalent, at least as far as the and gate goes.
I suppose I just need a slap up side the head, but am not seeing how it is supposed to work.
I don't know what this circuit is supposed to do, or if it works but...
with the two input AND gate, both inputs (counter Q2 and Q4 outputs) have to be high for the output to be high. So if either of the inputs go low, the output goes low.
with the diodes circuit: if the counter outputs Q2 or Q4 are high, then the common anodes of the diodes will be high. But if either Q2 or Q4 go low, the diode's anode will be at about 0.6 volts.
I don't know what this circuit is supposed to do, or if it works but...
I do not know if it works either, but it is part of a clock circuit. I apparently built it backwards and in order to find out if my logic is right, need to bring it back to the power supply. I used up my and gates with the displays so instead of adding another IC I figured it would be better to just add a couple diodes, and a resister.I guess what is hard for me to understand is how the inputs have a potential, if that makes sense.
If current flows though a diode, the anode (the left ends of the diodes in your schematics) is 0.6V higher than the cathode (the right end).
If, say Q2 is LOW, current will flow through D7, so its left end will be at 0.6V. This end is connected to PE so PE will also be LOW. In this case there will be a small current flowing from +9 through the resistor R6 and through D7.
Same thing happens if Q4 is LOW (with D6).
If both Q2 and Q4 are HIGH then no current flows through either diode, so the resistor R6 pulls PE HIGH.
(Another perspective... if no current flow through either diode, then no current will flow through R6. So the voltage drop across R6 will be 0 which means PE will be at +9V.)
I think I understand. Hopefully it will sink in with sleep.
Thanks
Mmm, sorry, that circuit is pretty ugly and I don't mean the diode version.
What it is is a divide-by-6 counter with carry out.
What it's doing is detecting the counter is 6 (that means Q4 high and Q2 high) then sending a reset to the counter.
The CD4510B has an asynchronous reset.
That means that when the reset (or parallel load) happens it immediately jumps.
That means that the time when the counter is 6 is just a fraction of a second.
It counts: zero ..... one ..... two ..... three ..... four ..... five ..... six-oh-no-six-is-bad!-reset-quickly-zero ..... one
The problem is, when it gets the reset command what if Q2 resets before Q4?
Then the logic that is driving the reset will relax and Q4 might not get reset.
Who knows how well/reliably this circuit will work.
In ye olde days when we did this kind of thing we used a monostable (one-shot) to make sure that the reset pulse was long enough.
Also, the carry out on your circuit goes low on the counter=5.
U2.4 is not doing anything useful since it inhibits only on counter=6 which means the counter=5 condition is already failed.
In any case, with the asynchronous reset, who can know exactly how this circuit reacts.
The thing to do is to use something modern with a synchronous reset (maybe a 74HCT163?).
Then you can detect counter=5 (Q4 is high, Q1 is high) and use that as both your carry out and your synchronous reset.