Hello, everyone !
I looking for V reg. for amplifier and stumble across some draft ... then I simplified it to the bare-bone ...
And i have no clue how it works ... I swear ... I tried to understand ...
it does keep Vout == Vzener + Vbe ... regardles of load ... but how
?? Second point Vout should be at least 10V below Vin - not really efficient ...
Can someone explain ... it itching me
sim file:
https://www.justbeamit.com/5wrif
Easy explanation, 3 inverting stages makes a stable circuit. Note that the mosfet is channel P and source at the inputnis working as common.
Voltage goes up as output load is discconected, the base of the lower transistor goes up, the collector and base of tge upper bjt goes down, collector of this second transistor goes down, gate goes up, less current at the drain, output voltage goes down.
JS
Thanks, it seems I got confized by Q3, re-draw it ... it more understandable now ...
Now it looks like drop voltage should be pretty low, maybe check the values as you don't need much drive current to the gate, just enough low impedance so is fast enough to react to input and output changes.
JS
OK, so .... here is some final , a standard compensating ...
2 things if someone clarify, make sense :
Q1, Q2 - darlington , reason to decrease load on opamp, therefore maximize slew rate ....
R8, R9 - mosfet linearizaion , from Bible, ?
maybe other suggestion, (transistor type will look at , at least 100V Vce )