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Hello,
I am relatively new to electronics and one of my first project to build a generic and flexible buck/boost converter based on TPS63030 (http://www.ti.com/product/TPS63030). Hope that it might be useful and efficient enough in prototypes (on breadboard as well as separately) with output 50-150 mA range and possibility go up if required.
I tried to follow TI recommendations and looked into their TPS63030EVM-417 (http://www.ti.com/lit/ug/slvu275/slvu275.pdf) and TPS63030EVM-658 http://www.ti.com/lit/ug/slvu391/slvu391.pdf user’s guides, although doubled a number of resistor dividers (2 in series except just one) for output voltage adjustments. Not sure if it will have a negative impact, but thought provides a room for manoeuvre and further adjustments.
Please comment my lousy schematic and layout (both attached), would appreciate for your input, criticisms and suggestions.
Many thanks
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Question, why is the FB divider made from 4 resistors?
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Not bad! Seems to be a perfectly reasonable layout.
I might recommend, if I had to recommend something, spreading the ground plane on the back over the entire board, and adding some more vias stitching together the top and bottom grounds. But the grounding is already decent.
Okay, I didn't notice, you did ask for comment on the schematic too. That is awful, to be frank. No offense.
You should arrange the symbols in something representative of the actual function of the circuit...
Here's one I did recently. It's not the world's tidiest, but it's way better. You can see the flow of power through the input circuit - polarity protection, a filter, then the input capacitors, and into the controller. Through the controller, the inductor, the output caps, output filter..... It actually follows a path.
You just seem to have stuck things places they fit. -
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Question, why is the FB divider made from 4 resistors?
Having done similar, I'd say the idea is for getting different values from a fixed number of value resistors you may have on hand, and/or to fine tune the voltage with large value resistor(s) placed in parallel. If your voltage was a tad low, you could place a high value trim resistor on one of those pads to tune the output. You can also put a small proto-board area on the pcb in that spot - a bunch of pads with little traces that can be cut, so you can link resistors in series and/or parallel. -
I suggest flipping C6 horizontally and saving a via this way by connecting the capacitor directly to the ground pin of the chip right next to Vin A . This would also allow that trace to go straight down instead of wiggling its way around.
There's no minimum for input capacitance, as long as it's at least around 4.7uF ... I would suggest going with 22uF rated for 25v at least, x7r ... or 2 x 10uF ... in some cases due to voltage bias a single 10uF may be too little ... see https://www.maximintegrated.com/en/app-notes/index.mvp/id/5527
If you flip that C6 capacitor you may be then able to also thicken out the voltage and ground traces ...
You could use a couple of 1206 0 ohm resistors to save you from having that Vin trace go around or to save you from using the back of the board for that feedback trace..
I agree with the others about the 4 resistors for feedback while only two would be needed. Maybe you want to add a trimpot or something in parallel with a resistor for fine tuning?
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The layout is a nice low-inductance one. I can't see anything that would prevent it from working and it will likely work well. On my layouts I tend to pickup the FB path on the last capacitor to minimize the FB noise from the SW node of the circuit. Kind of splitting hairs though.
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Your layout looks well done. But I do suggest you make the whole bottom layer a ground plane. Vin and Vout will have even better coupling to the ground in that case when it comes to high frequency currents.
Since you have two layers, why not dedicate the bottom layer to 0V/GND only. Make it one big GND plane, and use multiple (large) vias to connect components to it.
This way you don't need the trace between Vout and R6 on the bottom layer. In addition Vin to R1 can be a very short link too. Where you have space left on the top, pour ground and stitch it with multiple vias to the bottom layer.
Yes, vias do have a bit of inductance, so you get a bit more there. Yet you reduce trace inductance by a lot at the same time. Especially when all traces have the reference plane right below them. Do keep vias relatively large and use multiple in parallel. Your electrons will thank you
Finally, in case you mount the PCB in a conductive enclosure; make sure you connect the enclosure directly to the reference plane (0V/GND). In that case use plated holes for your mounting holes directly connected to the plane. -
rx8pilot, c4757p, KL27x, mariush, Christe4nM - many thanks for the feedback, much appreciated.
@c4757p - Yes, that’s right, the schematic was a big mess
, so I updated it and hope it's become better than before, please see attached v2.
Before I will apply major changes in PCB layout, would be great to clarify following:
FB 4-resistors:
As mentioned by KL27x, the idea is to use different values to try to find “ideal” resistance to make an output voltage as much accurate as possible and to be honest I only considered resistors in series. KL27x suggestions (re a small proto-board area) are food for thoughts, just need to find a good example how it can be done nicely.
Also, looking into SLVA423 (http://www.ti.com/lit/an/slva423/slva423.pdf) and taking into account that for low-powered converters the total resistance value goes towards 1M and above, thought that placing 180K~200K 0.1% resistor on both sides of FB and add 0.5% for above 330K to the final value, so these “manipulations” can save me 1% accuracy assuming my math is correct
(compare to 1% generic resistor). Please correct me if I am wrong.
Does it make any sense or unnecessary waste resources?
What would be side effect 4-vs-2 resistors?
Feedforward capacitor:
I started to dig a bit deeper in DC/DC world and found so called “feedforward capacitor” , would it make sense to add Cff as optional if extra a fine-tuning might be applied later?
Vin/Vout caps:
10uF 0603 X7R - it seems that choice is very limited. What would be impact if I will replace these C1-C4 with 0805? Or maybe 1 Vin(C1) /2 Vout (C3,C4) 0805 10uF as required and 1Vin (C1)/1Vout(C5) 0603 as optional?
C6: flipped- much nice fitted now, imho
Vin trace around: moved temporarily (or permanently, depends from GND outcome) to the bottom layer
GND /stitching:
As suggested, a big ground plane that sole/partially dedicated to GND and stitched - would these contradict to TI recommendations?
As per TPS63030 spec: “Therefore, use wide and short traces for the main current path and for the power ground tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a common ground node for power ground and a different one for control ground to minimize the effects of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC!”
Top GND plane vs 2 GND vias: not sure if it's good idea, please see attached "TopGND_vs_2Vias"
Does it Make Difference?:
as attached "DoesItMakeDifference"
Mounting holes: What would be right size for this board? At the moment, M2. What about plated holes or not?
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re: schematic
I made the mistake at R1 , directly tied to Vin, that's fixed now and the update has been attached.
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As mentioned by KL27x, the idea is to use different values to try to find “ideal” resistance to make an output voltage as much accurate as possible and to be honest I only considered resistors in series. KL27x suggestions (re a small proto-board area) are food for thoughts, just need to find a good example how it can be done nicely.
Well, if my post was a little confusing, it's because I thought you had set up a second set of pads in PARALLEL. That was just my own personal bias, I think; that's more likely the way I would have done it. But having two sets of pads in series is good, too. (You can always stack SMD resistors to get more than one in parallel, anyhow).
As for making proto-area, just as one example, you could bridge your auxiliary set of series resistor pads with a 10 mil trace, in case you get a perfect output with just two resistors. Cut the trace, only if you need to add the second resistor! That may save a little trouble over having to use 0 ohm jumpers or 4 resistors by default.
Another way to do it is to have a second set of pads next to the main resistor divider pads. But these are just four lone, oversized square pads, not connected to anything. So you can either solder a resistor in parallel and bridge the ends of the resistor to the "main" resistor with solder blob jumpers. Or you could turn the resistors sideways to get two in series, and bridge the pads between the two resistors.
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GND /stitching:
As suggested, a big ground plane that sole/partially dedicated to GND and stitched - would these contradict to TI recommendations?
As per TPS63030 spec: “Therefore, use wide and short traces for the main current path and for the power ground tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a common ground node for power ground and a different one for control ground to minimize the effects of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC!”
The short version:
My recommendation for a big ground pour and connecting directly to it does not contradict TI’s recommendation. Basically TI are saying: make sure you connect the control loop/feedback components as close as possible to the GND-pin (pin 9). I suggest: do that while using a ground plane and you’re good.
The long version:
As you might know, every bit of conductor (a trace, a plane, a wire) has a certain resistance, inductance and capacitance. So when current flows through it, a little voltage drop occurs across said conductor.
Take the protective earth wire for example (green/yellow in Europe). In circuit theory we assume that is always at the 0V/GND potential. Yet in reality it is not at all. There are all kinds of leakage currents flowing through it. Those currents are at all kinds of low and high and very high frequencies. Somewhere the earth-connection gets to a pin that is driven deep into the real earth (the dark sandy & muddy stuff). If you’d take that point as reference and measure the voltage across the earth wire at several points along its length you’d be surprised. Both at the levels as well as at the high frequencies present.
OK, so far the example, now back to your circuit. Your power conductors: Vout/GND pair (for example) will see relatively large current flow through them. In addition, it being a switching power supply, there will be high frequency content too. These will create (noise) voltages across the conductor. Yet for the control loop it is important that the reference (GND in this case) is a good clean reference. If you connect the feedback and control loop components almost directly to the IC’s GND/reference pin, you make sure that noise voltages have almost no effect. This way the control loop sees a steady and clean reference. This is what TI is telling you to do.
Now why a ground plane? Well, by nature (physics), currents travel in loops, and want to travel in the smallest loop possible. As it turns out this really great for us when it comes to EMC/noise/interference. The closer the ‘send’ and ‘return’ currents are to each other, the better they couple to each other, the easier they experience the path, the more they want to take it. The better they couple, the less they couple to other signals/conductors where they become unwanted (noise) currents. The easier the path, the less likely they take different routes, giving rise to potential noise/problems. This is valid for all currents at all frequencies above say 1 kHz.
(Below that it’s still valid in a way, but current tend to take the path of least resistance. While above say 1 kHz currents take the path of least impedance, which is mostly governed by the inductance present. Closely coupled ‘send’ and ‘return’ conductors have very low inductance as it ‘cancels out’)
If we can make the wanted currents have the best path possible, the less likely they are to turn into unwanted currents somewhere else.
Also, current flowing in a loop gives rise to inductance; the larger the loop, the larger the inductance of the loop; the more easily the current couples into other parts of the circuit.
The best way to create that easy path (with good coupling thus low impedance) is by providing a nice large copper plane right below all traces (whether small or wide, signal or power). This way the currents can go anywhere they want: i.e. they will stay right below their ‘send’ conductors by nature. Which, as said, is really great as it will prevent unwanted coupling, noise, and EMC problems for a large part.
So how do the two, GND plane and TI’s recommendation, come together? Well, first by providing the plane you help the currents flow in the smallest loops possible; potentially existing unwanted currents also have the shortest path ‘home’; so noise voltages are kept to a minimum. In addition, you make sure you connect the feedback/control loop components to the GND plane right at the GND pin of the IC. When all currents (ideally) stay right below their own ‘send’ conductor, you have a nice clean reference.
Misc. notes:
• The wider a trace, the lower its resistance & inductance per length. The longer a trace, the larger its inductance.
• ‘Paracitic’ inductance in not helping us: non-dc currents through an inductance give rise to voltage drops, i.e. noise voltages in our case here.
• Vias are a conductor too, so they also have resistance, capacitance and inductance.
• Multiple vias in parallel result in a lower total inductance; Larger vias have lower inductance tooMounting holes:
What would be right size for this board? At the moment, M2. What about plated holes or not?
My personal preference is to go no smaller then M3. I don't really know what's standard.
When it comes to plated and connected to the ground plane or not:
Suppose you have an enclosure that is conductive. There is a change that bits of high(er) frequency currents couple into the enclosure. If you connect the enclosure to the plane directly you provide a low-impedance path for those currents to flow ‘home’; the loop area stays as small as possible etc. etc.
Suppose you want to know more?
Or in more detail:
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KL27x, Christe4nM - much appreciated for your comments
I updated a bit schematics - added R7 parallel resistor for FB-Vout net and made changes in both layouts (attached), so there is a big GND on the bottom layer.
Does that make sense?
Christe4nM - many thanks for the compreshensive information and details, there are a lot to learn!
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Hi,
Didn't look at the circuit in detail, but a couple of layout comments.
I don't like fills directly on pins - use thermal reliefs wherever thermal/electrical reasonablness allows - the reasons for this are two-fold. Firstly to ease the even heating of the pins/reflow solder etc, but also because you probably are using copper-defined pad shapes (rather than mask-defined shapes) - using mask-defined shapes for fine pitch relies on very good registration between the solder mask and the pins, which you might not have.
You might like to extend the shapes around the inductor to provide some thermal dissipation through the PCB. Sometimes, those inductors get toasty, and a few cm of copper around them can help. Again, use thermally-relieved pours.
Best regards,
Nathan