I bet there wasn't an adapter for bubble memories either - but there wouldn't have been much point! Which reminds me that I've still got some Intel bubble memory iSBCs somewhere. Wonder how hard it would be to get them running?
I have a Data I/O Chiplab 32 with only DOS software so haven't really used it much....so I've had this state of the art programmer sitting on the shelf for years. I have tried to find the windows based software many times but to no avail.
The conductive pad reminds me of a conductive adhesive transfer tape that I use at work which allows for discrete segments of electrical conduction through the z-axis but not across the plane.
The gold color comes from the fact that it used very fine gold wires. These wires were aligned vertically through the pad during the manufacturing process. The wires do not merely travel strait from top to bottom but use a uniform radius curve.
The UniSite project goal was to create a programmer that would last 10 years and program every part that ever existed.
As you pointed out it lasted far more than the 10-year goal and here is why:
The UniSite actually has two processors and the 2nd CPU is likely the reason the UniSite was so unique and powerful.
The mother board includes the 68000 CPU and a portion of the 2nd processor which is a distributed “Pin Processor”.
The 10MHz 68000 you noticed runs the GUI and operating system and was considered a high-end “Work Station” processor at the time.
The H&R EPROMs you noticed are the boot for the Hunter & Ready Real Time Operating System.
The main DRAM grouped near the CPU was designed to be twice as big as the software developers requested.
Before we shipped the first unit the software outgrew the RAM and I had to scramble and build a RAM expansion board.
Fortunately we did plan for a CPU bus expansion connector and daughter board which the RAM board utilized.
The RAM board design and layout was completed in about a week of late nights between me and the layout designer and it fortunately worked on the first go.
The RAM design uses a custom PLD state machine I created to refresh and provide timing between the Dynamic RAM and 68000.
The brand new (at the time) 720K floppies were controlled by a new floppy controller with the first digital data separator (no external parts).
The serial ports included a feature you noticed which I named “Smart Port” to switch between DTE and DCE along with an LED to indicate a valid connection.
Customers often wired the serial interface wrong so this allowed the ports to work with the most common wiring combinations.
The PCBs were the first in the company to be designed using Signal Integrity design methods (series and parallel termination of fast logic) which I was just learning.
The UniSite passed radiated emissions testing on the first try and the testing manager credited the signal integrity design work for reduced emissions.
Because of the SI concepts gained while working on this product I later went on to start a software company called “HyperLynx” now part of Mentor Graphics.
The ferrite bead you noticed attached to the 68000 was required to correct a flaw in the 68000 processor’s DIP package power structure.
Instead of putting the power pins in the middle of the chip near the die the 68000 designers put the power pins out near the corners.
The corner power pins added so much package inductance the die bounced causing glitches on the address strobe.
I added a ferrite bead and series resistor to filter out the majority of the glitch and this resulted in stable operation.
This became a well-known issue with the DIP version of the 68000 but it wasn’t mentioned in the design documents at the time.
I spent hours with a scope and analyzer trying to figure out where this glitch was coming from.
Fortunately Data I/O was interviewing an engineering manager candidate who had worked directly with the 68000 development team.
As luck would have it he walked by when I was working on the problem and we talked about the issue.
He explained that Motorola had acknowledge the ground bounce issue and I would need to filter the strobe.
The bead and resistor filter worked perfectly and saved a major redesign.
The core of the Pin Processor is the Toshiba mask programmed “Gate Array” you notice.
For a number of years the UniSite was the fastest programmer in the market and the Pin Processor is likely the reason.
Data I/O’s best programming guru brainstormed with us for weeks to create the concepts that evolved into the pin processor.
We did not have FPGAs available to us when the UniSite was designed so the only other choice was a mask programmed “Gate Array”.
The Gate Array had to work on the first try due to the high cost of a mask spin and our release schedule requirements.
My team worked on the pin processor and gate array design and we simulated for almost two months of 16 hour days, 7 days a week.
Every logic transition of every gate was exhaustively simulated.
The pin processor also includes a number of PLD and RAM chips on the main board.
The Pin Processor is one of the few variable word width processors I am aware of and may be unique in the world.
Each Pin Driver board drives 4 pins as you guessed. A Gate Array chip on each pin driver board provides four pins worth of processor expansion.
A processor word may be hundreds of bits wide and for a long time the pin processor speed and accuracy blew away all other programmers in the market.
The Pin Processor includes a Ram based sequencer made of 74F logic, PLDs and dual ported static ram attached to the 68000 (see schematic).
The Pin processor forms an associative CPU where each pin has a slice of the processor logic and responds to events in parallel with all other pins.
The Gate Array has a mode select pin “4 pin universal” and “16 pin logic only”.
The instruction word for the Pin Processor also contains a high-accuracy timer setting the time between each word executed (nanoseconds to milliseconds).
The pin processor allowed a single byte write or read operation to route to any 8 pins on the device under test or any set of 8 pins on any number of devices.
I was given permission to disclose the above to a number of sales teams responsible for selling the UniSite so they could discuss the UniSite with their customers.
This placed the limited information above into the public domain.
At the request of Data I/O management I filed for a patent on the processor but due to the limited amount Data I/O wished disclosed we failed to get a patent.
It was too complex to explain the processor concept in a patent without disclosing the instruction and design details.
The examiner said I can tell you have something unique but we cannot grant a patent on it unless more of the concept is disclosed.
The “Programming Guide to the Galaxy” manual with all the pin processor details and instructions was about an inch thick and was never made public that I am aware of.
The ferrite bead you noticed attached to the 68000 was required to correct a flaw in the 68000 processor’s DIP package power structure. Instead of putting the power pins in the middle of the chip near the die the 68000 designers put the power pins out near the corners. The corner power pins added so much package inductance the die bounced causing glitches on the address strobe. I added a ferrite bead and series resistor to filter out the majority of the glitch and this resulted in stable operation.
This became a well-known issue with the DIP version of the 68000 but it wasn’t mentioned in the design documents at the time.
QuoteThe PCBs were the first in the company to be designed using Signal Integrity design methods (series and parallel termination of fast logic) which I was just learning.
The UniSite passed radiated emissions testing on the first try and the testing manager credited the signal integrity design work for reduced emissions.
Is that worth a small extra video? I'm sure some will find it of interest. Apart from me.
Info from on of the original design team who emailed me