Highest and Lowest voltage PROMs?

• Highest and Lowest voltage PROMs?
  Posted by colejohnson66 on 10 Nov, 2019 17:50
• I’m curious what the highest and lowest voltages required to program a PROM are.
  
  According to Wikipedia (and the linked data sheet), first generation Intel 1702A EPROMs required -48V(!) applied to the substrate to program. The article then mentions that second generation EPROMs required +25V programming voltage pulses.
  
  Is there any PROM (one time programmable, EPROMs, E²PROMs, etc.) that required even higher or lower voltages than those two early EPROMs?
• #1 Reply
  Posted by SeanB on 10 Nov, 2019 18:16
• Probably not, the first generation devices were really weird with supply voltage, and also were picky about supply sequencing as well. Later ones simplified it by having on die bias generators to simplify things, and also easing the need to have power rail sequencing, plus they were not as prone to latch up and self destruction. As a bonus they also got more erase cycle endurance, the originals were rather notorious for getting flaky with only 100 cycles on them or less, simply because they were so new, and also for getting bits that would never program down to a 0 level either.
• #2 Reply
  Posted by T3sl4co1l on 10 Nov, 2019 19:46
• Lowest is easy, modern Flash runs on quite low external voltages, and 2.7V (and lower?) stuff has been around for many years.
  
  Although, there's an internal charge pump which boosts this to whatever is still required (I think 4-6V for the highest density stuff??), which may be what you're after.
  
  Programming current is another excellent question; as far as I know, fuse PROMs required quite a gulp (~100mA?).  Others?
  
  Tim
• #3 Reply
  Posted by colejohnson66 on 10 Nov, 2019 20:52
• I probably should’ve been more clear when I said “lowest.” I meant lower below ground than -45V. But 2.7V would probably be the closest to ground. Unless there’s 1.8V and below flash memories.
• #4 Reply
  Posted by SiliconWizard on 10 Nov, 2019 21:06
• I don't know of any PROM/EPROM requiring lower than -48V (as with the earlier PROMs), at least for commercial chips.
  
  As to modern Flash memory, as T3sl4co1l said, they usually have an internal charge pump, so they are actually programmed with around 5V at least internally. I don't think you can reliably program Flash memory cells with current technology *directly* with 2.7V or lower. There *are* 1.8V Flash chips (eg: W25Q32JW). But they are using internal charge pumps as well.
• #5 Reply
  Posted by edavid on 11 Nov, 2019 04:14
• The MM5203 required -50V for programming.
  
  The 2708 required a nominal +26V, but +25V would also work.
  
• #6 Reply
  Posted by techman-001 on 11 Nov, 2019 06:23
• Quote from: edavid on 11 Nov, 2019 04:14

  The MM5203 required -50V for programming.
  
  The 2708 required a nominal +26V, but +25V would also work.
  

  
  That brings back memories from 1975 
  
  I've had to build programmers for both these chips, but the MM5203 was the most nerve wracking because they were so expensive to blow up back in the day.
  
  And I blew up a few getting the programmer working properly.
  
  The programmer had to be made with TTL and analog parts because I didn't have a handy MCU to throw at it like nowadays.
  
  Here is a  online scan of the MM5203 programming process for any other 'greyhairs' wanting a walk down memory lane.
  https://archive.org/stream/bitsavers_nationaldaMemoryDatabook_43572148/1977_National_Memory_Databook_djvu.txt
  
  Operation of the MM4203/MM5203 in program mode
  
  Initially, all 2048 bits of the MM4203/MM5203
  are in the HIGH state. Information is introduced
  by selectively programming LOWS in the proper
  bit locations. (Note!)
  
  Word address selection is done by the same decod-
  ing circuitry used in the Read mode. The eight
  output terminals are used as data inputs to deter-
  mine the information pattern in the eight bits of
  each word. A LOW data input level (-50V) will
  leave a HIGH and a HIGH data input level will
  allow programming of a LOW All eight bits of one
  word are programmed simultaneously by setting
  the desired bit information patterns on the data
  input terminals. The duty cycle of the Vdd pulse
  (amplitude and width as specified on page 4)
  should be limited to 2%. The address should be
  applied for at least 1 jus before application of the
  Program pulse. In programming mode, data inputs
  
  
  1-8 are pins 4-11 respectively regardless of the
  logic state of Ag and mode control. Chip select
  should be disabled (HIGH).
  
  Positive logic is used during the read miode for
  addresses and data out. Address 0 corresponds to
  all address inputs at V,l and address 255|o cor-
  responds to all address Inputs at V|^^. A “1" or a
  P at a data output corresponds to Vqh- A "0” or
  an N at a data output corresponds to \/Q^_. Posi-
  tive logic is also used during the programming mode
  for addresses. Address 0 corresponds to all address
  inputs at V,Lp and address 255 iq corresponds to
  all address inputs at V|Hp.
  
  Negative logic is used during the programming mode
  for data in. A "1" or a P at a data input corres-
  ponds to V|L,p. A "0” or an N at a data input
  corresponds to V|Hp.