Would it be a valid assumption to assume an EMI induced error would be approximately constant across input voltages?
The error rising along with input voltage seems to suggest some type of leakage, not sure where though.
Here's another idea, assuming the error IS linear with input voltage, would it be acceptable to add a very small amount of gain in the output opamp to account for the error? Or is this something that is better done in software?
Stray capacitance perhaps from the flying capacitor?
One of the differences between your cirquit is that your flying capacitor is much larger than my WIMA MKS 02 (2.5 mm raster) 1uF.
Perhaps your capacitor has a "outer foil" which is on the wrong pin.
So I would try first to swap the pins of the capacitor and then try a smaller one.
I usually handle such things in software (EEPROM coefficient).
For a fixed 5V reference out of 10V I would do a overall adjustment
of the 10V Reference (at the trim pin) in a way that the 5V fit.
with best regards
Andreas
Edit: did you measure the frequency of the LTC1043?
You should have something around 400-500 Hz.
Quick question- in the article, is this the RC filter you are referring to?
What I understand you saying, is if Cl has a large enough ESR, then Rl isn't necessary. If Cl ESR is too low, then add a small resistor in series with Cl? Or a shunt resistor as pictured?
Only 250 Hz. Maybe this is the problem? When I built this circuit I know put the correct capacitor value in for oscillation pin, but I will unsolder it and measure to verify.
That is right and a resistor is placed in series with the capacitor. For a standard aluminum electrolytic or tantalum capacitor, this resistor already exists in the form of the ESR.
The idea is that the output resistance of the operational amplifier combined with the shunt capacitance lowers the open loop gain below 1 before the feedback reaches 360 degrees. The ESR or series resistance adds some phase lead making this easier to accomplish and also prevents parasitic oscillation of the output stage.
It is the brute force way to accomplish this but at least in my experience, it actually provides better performance.
I am closing in! The data doesnt seem as linear this time, almost like there are two "levels" or plateaus.
It is possible to build a charge pump with other, higher voltage CMOS switching chips (e.g. DG411 or similar) and a suitable clock. However other chips tend to have a higher charge injection and thus a slightly higher error is expected. There might be newer ones with comparable performance, though usually without the internal clock.
The error has three main contributions: Loading by leakage / input currents to the DMM/OP, parasitic capacitance and charge injection. So one can not expect a perfect division, but a rather stable one. The charge injection may show a nonlinear dependence on the voltage. Parasitic capacitance should be mainly proportional or constant (coupling to control lines). The loading effect would be about linear in the load.
The other way would be to use a 2nd source in series to the instrument as zero Voltmeter in 100mV range and compare both partial voltages on the LTC1043.
(from input to output and from output to gnd).
with best regards
Andreas
Another way to design a high precision charge pump is to use optically pumped switches in the form of either LDRs (light dependent transistors) or photo FETs. Optical coupling reduces charge injection significantly.