Everyone has an opinion on languages, personally I like VHDL and find that it has the best hobbyist support. Verilog is the other big one, which you choose is largely a matter of personal preference. Anything that can be done with one can be done with the other.
When I was starting out the best book I found was a free one called Free Range VHDL. If you do a search online you'll find it.
The Multicomp was another very useful educational project since he provides a bunch of pre-written modules along with a top level file and instructions for putting it all together. That taught me how to assemble existing building blocks of code.
I would highly recommend getting a SoC fpga dev board, e.g. de0-nano-soc, because you can do so many fun things with implementing peripherals on the fpga and writing drivers for it. I've implemented video output devices, data streaming devices (for software defined radio), etc. You can also access dram through an AXI bus without the hassle of dealing with controllers or worrying about timings, as that is all configured for you by the bootloader.
For a beginner I would also recommend vhdl instead of verilog, as vhdl is intentionally designed to make it hard to make mistakes (with its strict type system and all that); once you get past the compilation errors your design usually works. With verilog you will be catching your errors on the hardware rather than at compilation time. Don't bother with simulations because once you start doing more complex designs it will be unusably slow and you will have to un-learn relying on it. Not to mention the simulated behavior often differs from the hardware, e.g. if you use processes the sensitivity list applies during simulation but is ignored in synthesis (and this is considered working as intended!). Learn the logic analyzer tools instead (signaltap for altera, chipscope for xilinx).
There are only a very few constructs you need to learn. Gates, registers, multiplexers and finite state machines (unless I forgot a couple). Once you know how to implement these constructs, the rest is just details.
Don't bother with simulations because once you start doing more complex designs it will be unusably slow and you will have to un-learn relying on it
I would highly recommend getting a SoC fpga dev board, e.g. de0-nano-soc, because you can do so many fun things with implementing peripherals on the fpga and writing drivers for it. I've implemented video output devices, data streaming devices (for software defined radio), etc. You can also access dram through an AXI bus without the hassle of dealing with controllers or worrying about timings, as that is all configured for you by the bootloader.
For a beginner I would also recommend vhdl instead of verilog, as vhdl is intentionally designed to make it hard to make mistakes (with its strict type system and all that); once you get past the compilation errors your design usually works. With verilog you will be catching your errors on the hardware rather than at compilation time. Don't bother with simulations because once you start doing more complex designs it will be unusably slow and you will have to un-learn relying on it. Not to mention the simulated behavior often differs from the hardware, e.g. if you use processes the sensitivity list applies during simulation but is ignored in synthesis (and this is considered working as intended!). Learn the logic analyzer tools instead (signaltap for altera, chipscope for xilinx).
"Don't bother with simulations" you are joking right?
I would highly recommend getting a SoC fpga dev board, e.g. de0-nano-soc, because you can do so many fun things with implementing peripherals on the fpga and writing drivers for it. I've implemented video output devices, data streaming devices (for software defined radio), etc. You can also access dram through an AXI bus without the hassle of dealing with controllers or worrying about timings, as that is all configured for you by the bootloader.
For a beginner I would also recommend vhdl instead of verilog, as vhdl is intentionally designed to make it hard to make mistakes (with its strict type system and all that); once you get past the compilation errors your design usually works. With verilog you will be catching your errors on the hardware rather than at compilation time. Don't bother with simulations because once you start doing more complex designs it will be unusably slow and you will have to un-learn relying on it. Not to mention the simulated behavior often differs from the hardware, e.g. if you use processes the sensitivity list applies during simulation but is ignored in synthesis (and this is considered working as intended!). Learn the logic analyzer tools instead (signaltap for altera, chipscope for xilinx).
"Don't bother with simulations" you are joking right?
For someone getting started, simulation is just another bunch of stuff to learn before the gratification of getting some hardware working.
As you get into more complex stuff and longer place/route cycles, at some point it will it become necessary but I've yet to feel any need for it it for the few, fairly simple stuff I've done to date.
One should always strive to do as close to professional grade work as possible
a.) Produces useless shit
b.) Doesn't do anything complicated.
For someone getting started, simulation is just another bunch of stuff to learn before the gratification of getting some hardware working.
As you get into more complex stuff and longer place/route cycles, at some point it will it become necessary but I've yet to feel any need for it it for the few, fairly simple stuff I've done to date.
I'm surprised, it must have been some very simple stuff, it only takes seconds to simulate if you not taking huge SoCs and millions of cycles and you can instantly see what is going on without having to guess and wait another tens of minutes to see if you were right
a.) Produces useless shit
b.) Doesn't do anything complicated.That's probably what I am aiming at.
I plan to look at Verilog, VHDL and simulation all in a probably very superficial way.
In my journey so far I am amazed how there seems to be a huge gap in the market between the expen$ive SoC FPGAs and the commodity processors with a bit of configurable logic.... e.g. a PIC with a CLC.
One should always strive to do as close to professional grade work as possible
Which implies simulating the design.
If we were interviewing someone for a position as an FPGA design engineer and that person said, "I don't think simulation is necessary," the interview would be terminated immediately.
Did Xilinx introduce non bga Artix parts? Remember sticking to ISE and Spartan on a project a while ago because of that.
For a beginner I would also recommend vhdl instead of verilog, as vhdl is intentionally designed to make it hard to make mistakes (with its strict type system and all that); once you get past the compilation errors your design usually works. With verilog you will be catching your errors on the hardware rather than at compilation time.
Don't bother with simulations because once you start doing more complex designs it will be unusably slow and you will have to un-learn relying on it. Not to mention the simulated behavior often differs from the hardware, e.g. if you use processes the sensitivity list applies during simulation but is ignored in synthesis (and this is considered working as intended!). Learn the logic analyzer tools instead (signaltap for altera, chipscope for xilinx).
I haven't found simulation to be all that helpful. Sure, it works for decade counters and things like that. Where my problems crop up is about a million cycles after the start when I don't properly handle the op code that's 1000 lines into the OS code. I know the system hangs but I might not know where so I don't know which op code.
So, one layer up, I write test code for each instruction and watch it execute on the LEDs. I might even build a hardware breakpoint capability into the FSM breaking on the address in the console switches and perhaps single-step from there.
In the early years, I didn't have a simulator with Xilinx ISE. I'm still working through whether it is worth the effort with Xilinx Vivado. The logic analyzer capability is pretty nice but it remains to be seen how well it works a million cycles in.
My projects are all hobby works. I try to avoid getting clever with the coding.
One thing I learned a long time ago: If I don't put bugs into the code, I won't have to spend time getting them out of the code.