I'm writing a USB 3.0 5gbps IP core right now. Minimal simulation.
Really, how do you simulate extremely complex and non deterministic behavior of a 5gbit PHY? You don't. I use embedded logic analyzer and my brain.
There is a small amount of internal logic I did verification against. But even then you're only verifying against what your brain can come up with, not reality, which is always nastier.
Now if all you're doing is plugging together various bits of licensed IP and maybe doing some internal logic, sure simulation might work there if the vendor provide a functional equivalent. But it's right out of the question many times.
Gospel is that you write a testbench... I just read a book about it (
"Writing testbenches - Function verification of HDL models" by Janick Bergeron - ISBN 0-7923-7766-4). If you can stare at hundreds of waveforms all day long and (hope to) find problems that way, you probably can also come up with a way to describe that functionality and capture it in a function model. VHDL and Verilog provide loads of non-synthesizable constructs to aid in that. You don't write RTL in a testbench of course.
I think ASIC companies won't commit a design to silicon without extensive testbenches that completely test a design and that allow regression testing. You simply can't test a complex design by staring at (captured) waveforms. And can you remember how they need to look like? Isn't there a specification document to which you can test your widget against? List of use-cases? Expected behaviour?
And what if there is no hardware available at all?
Gospel is that you write a testbench... I just read a book about it ("Writing testbenches - Function verification of HDL models" by Janick Bergeron - ISBN 0-7923-7766-4). If you can stare at hundreds of waveforms all day long and (hope to) find problems that way, you probably can also come up with a way to describe that functionality and capture it in a function model. VHDL and Verilog provide loads of non-synthesizable constructs to aid in that. You don't write RTL in a testbench of course.
I think ASIC companies won't commit a design to silicon without extensive testbenches that completely test a design and that allow regression testing. You simply can't test a complex design by staring at (captured) waveforms. And can you remember how they need to look like? Isn't there a specification document to which you can test your widget against? List of use-cases? Expected behaviour?
And what if there is no hardware available at all?
Absolutely correct. I have worked as an RTL design / verification engineer for major microprocessor companies throughout my career, and you can be absolutely sure that no chip; no matter how small; ever gets manufactured without a very extensive verification effort. Verification is the longest step in the design process of any modern SoC. Verifying a modern, state of the art x86 microprocessor is typically a two-year effort involving regressions with testbenches, random code generators and directed tests. There are usually 2-4 verification engineers (testbench writers/debuggers) per RTL design engineer (who writes the Verilog/VHDL logic); and design verification is usually the first career step for architects or RTL designers.
And there is a huge industry around this; as well as dedicated languages such as System Verilog, Specman etc. to write testbenches and checkers.
Even the smallest designs in the industry are verified in this manner through dedicated verification code (testbenches, checkers and random stimulus generators, etc.) It blows my mind that any FPGA/ASIC engineer can claim that a complex ASIC or FPGA implementation can be released to production without a well-planned verification effort through testbenches.
It blows my mind that any FPGA/ASIC engineer can claim that a complex ASIC or FPGA implementation can be released to production without a well-planned verification effort through testbenches.
You are absolutely right, however the circumstances under which I'm doing this are:
1. One man operation
2. Produced under gubbmint R&D funding on a shoestring budget
3. Experimental and research driven
Verification IP ain't in the cards, so I'm doing what I can with unit tests and live protocol analysis.
You are absolutely right, however the circumstances under which I'm doing this are:
...
My comment was not specifically directed at you, sorry if it sounded like that. I just took a peek at your Web site and was thoroughly impressed, I have little doubt that you figured out a way to do a sufficient baseline level of verification through your unit tests.
I found it distracting, but maybe other people find the music helpful. Only more feedback will tell. 
+1 for distracting
Unless I'm absolutely desperate I will stop watching any such video with background music.
New video! VGA interface in Vhdl+simple game!
PLEASE stop the music - you're spoiling an otherwise good tutorial.
<duckingforcover>
the music is louder than the talk. Is it the theme music from LSL1?
</duckingforcover>
Yup, due to the music I couldn't make it past the first minute.
Lol, the intro music dissapear after 40sec. Then it gets not so loud and almost disappear when i speak. Otherwise the video will get lots of silence...which is really stupid.
I know the music goes smoother after half a minute, but by that time I had to subdue three impulses to close my browser. It seems that the frequency of the music you are using resonates with my flimsy computer speakers and with my skull. I'm still recovering.
Is it possible to only use one channel Left/Right to add background music and voice narration on both channels. Wouldn't this leave your audience the option to listen to voice only - granted in only one speaker.
Lol, the intro music dissapear after 40sec.
By then you're too late. As a viewer I have no way to know how long I'll have to endure the horrid music, so I just close the browser.
As a real interested viewer you will certanly stay longer, because you would really want to know how to program vga in vhdl. ..and you wouldnt give up so fast:)
As the others, I didn't like the intro music. But I'm a fan of ambient music and the video kept my attention because I know nothing about VHDL. It seems simpler than C??
Yes, i admit, the intro music in all my videos i a bit funky, but i think should drag viewes attention. At the beginning a wanted to use " Röyksopp - In Space" as background music, but they wanted about 1000 euro for no-commercial usage in youtube:(
Yes, i also find vhdl easier then C, especialy the syntax and all those pointers....
As a real interested viewer you will certanly stay longer, because you would really want to know how to program vga in vhdl. ..and you wouldnt give up so fast:)
Keep telling yourself that. The rest of the world judges a vid real quick, closes it when annoying, and hops on to the next one that doesn't suck. Welcome to the internet.
Why watch annoying vids when the people at Doulos have
VHDL and other HDL material that is not annoying.
Just watched it, besides the background music, I wonder why did you use Qsys to generate the PLL function instead of just using MegaWizard Plug-In manager to generate variation of PLL megafunction? Same result and input dialogs but I think that MegaWizard is recommended by Altera. Unless of course if one wants to instantiate the whole Qsys component.
Regards,
Janne
Oh, cmon, as I did my first steps in FPGA/VHDL i searched LOTS of websites and videos for clear, undestandable, practical tutorial from scratch (like my videos for example).
Most of youtube "tutorials" should be called " demos" , because they don't teach you anything.Also Doulos hasn't got any real tutorials for VHDL/FPGA. Just naked theory.
My videos are more educative then entertaining (unlike Dave's blog, which became more entertaining then educative with time, but this is another story).
That is why i am concerned, if anyone has found my video , then he surely want to learn something, and not just spend 10-15 Min watching random interesting video while eating.
In this case he will see that my video is long, the thumnail is showing the real result, there is source code=> everything is pointing that he will find what he looked for.So he would stay or at least rewind the intro.
"he rest of the world judges a vid real quick, closes it when annoying"-- that behaviour is more likely for someone, who dont search for anything in particular..more like cats video or fail compilation...
Just watched it, besides the background music, I wonder why did you use Qsys to generate the PLL function instead of just using MegaWizard Plug-In manager to generate variation of PLL megafunction? Same result and input dialogs but I think that MegaWizard is recommended by Altera. Unless of course if one wants to instantiate the whole Qsys component.
Regards,
Janne
I heard that megawizard was replaced by Qsys, but i am not sure. Anyway it will lead you to the same result;)
Oh, cmon, ...
In the end they are your video's. You can make them as you please. If we think we can do better, we should proove that. And as viewers, we'll make up for ourselves if we watch them or not.
I heard that megawizard was replaced by Qsys, but i am not sure. Anyway it will lead you to the same result;)
I think it was SOPC builder which was replaced by Qsys, MegaWizard is a quite different thing (and also used internally by Qsys).
Regards,
Janne