I don't have your chip so I cannot tell you how it will work on a F05.
However, I tried the following on a F03 chip and it works as expected.
Here is the code:Code: [Select]#include <stm32f0xx.h> //stm32f030f4
#include "stm32f0xx_rcc.h" //we use rcc
#include "gpio.h"
//connection
#define LED_PORT GPIOA
#define LED_A (1<<1)
#define LED_C (1<<2)
void SystemCoreClockHSIPLL2(uint32_t RCC_PLLMul_x) {
RCC_DeInit(); //reset rcc
RCC_PLLCmd(DISABLE); //disable PLL
RCC_HSICmd(ENABLE); //enable hsi;
RCC_HCLKConfig(RCC_SYSCLK_Div1); //set sysclk divider
//RCC_PCLK1Config(RCC_HCLK_Div1); //set pclk1/2 dividers
//RCC_PCLK2Config(RCC_HCLK_Div1);
/**
* @brief Configures the PLL clock source and multiplication factor.
* @note This function must be used only when the PLL is disabled.
*
* @param RCC_PLLSource: specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source
* @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
* @arg RCC_PLLSource_HSI48 HSI48 oscillator clock selected as PLL clock source, applicable only for STM32F072 devices
* @arg RCC_PLLSource_HSI: HSI clock selected as PLL clock entry, applicable only for STM32F072 devices
* @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
* PLL source).
*
* @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
* This parameter can be RCC_PLLMul_x where x:[2,16]
*
* @retval None
*/
RCC_PLLConfig(RCC_CFGR_PLLSRC_HSI_Div2, RCC_PLLMul_x); //configure pll / divider. _x=[2..16]
RCC_PLLCmd(ENABLE); //enable pll
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) continue; //wait for pll to be ready
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); //set pll as sysclk
while (RCC_GetSYSCLKSource() != RCC_CFGR_SWS_PLL/*0x08*/) continue; //wait for PLL to be ready
SystemCoreClockUpdate(); //update SystemCoreClock
}
//delays some
void delay(uint32_t dly) {
while (dly--) NOP();
}
int main(void) {
mcu_init();
SystemCoreClockHSIPLL2(RCC_PLLMul_12); //go to 48Mhz
PIN_SET(LED_PORT, LED_A); PIN_OUT(LED_PORT, LED_A);
PIN_CLR(LED_PORT, LED_C); PIN_OUT(LED_PORT, LED_C);
while(1) {
PIN_FLP(LED_PORT, LED_A | LED_C);
delay(100000);
}
}
In addition to SystemCoreClock, the speed at which the led is blinked varies visibly as I change the PLL multiplier.
So your issues are probably somewhere else.
#include <stm32f0xx.h> //stm32f030f4
#include "stm32f0xx_rcc.h" //we use rcc
#include "stm32f0xx_gpio.h"
//connection
#define LED_PORT GPIOF
#define LED_A (1<<6)
#define LED_C (1<<7)
void SystemCoreClockHSIPLL2(uint32_t RCC_PLLMul_x) {
RCC_DeInit(); //reset rcc
RCC_PLLCmd(DISABLE); //disable PLL
RCC_HSICmd(ENABLE); //enable hsi;
RCC_HCLKConfig(RCC_SYSCLK_Div1); //set sysclk divider
//RCC_PCLK1Config(RCC_HCLK_Div1); //set pclk1/2 dividers
//RCC_PCLK2Config(RCC_HCLK_Div1);
/**
* @brief Configures the PLL clock source and multiplication factor.
* @note This function must be used only when the PLL is disabled.
*
* @param RCC_PLLSource: specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source
* @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
* @arg RCC_PLLSource_HSI48 HSI48 oscillator clock selected as PLL clock source, applicable only for STM32F072 devices
* @arg RCC_PLLSource_HSI: HSI clock selected as PLL clock entry, applicable only for STM32F072 devices
* @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
* PLL source).
*
* @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
* This parameter can be RCC_PLLMul_x where x:[2,16]
*
* @retval None
*/
RCC_PLLConfig(RCC_CFGR_PLLSRC_HSI_Div2, RCC_PLLMul_x); //configure pll / divider. _x=[2..16]
RCC_PLLCmd(ENABLE); //enable pll
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) continue; //wait for pll to be ready
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); //set pll as sysclk
while (RCC_GetSYSCLKSource() != RCC_CFGR_SWS_PLL/*0x08*/) continue; //wait for PLL to be ready
SystemCoreClockUpdate(); //update SystemCoreClock
}
//delays some
void delay(uint32_t dly) {
while (dly--) asm("NOP");
}
int main(void) {
SystemCoreClockHSIPLL2(RCC_PLLMul_12); //go to 48Mhz
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOF, ENABLE);
GPIO_InitTypeDef gis;
gis.GPIO_Mode = GPIO_Mode_OUT;
gis.GPIO_OType = GPIO_OType_PP;
gis.GPIO_Pin = LED_A | LED_C;
gis.GPIO_PuPd = GPIO_PuPd_NOPULL;
gis.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(LED_PORT,&gis);
LED_PORT->ODR &= ~(LED_A | LED_C);
while(1) {
LED_PORT->ODR ^= (LED_A | LED_C);
delay(100000);
}
}
the chip resets when i enable the PLL..
#include <stm32f0xx.h> //stm32f030f4
#include "stm32f0xx_rcc.h" //we use rcc
#include "stm32f0xx_gpio.h"
#include "stm32f0xx_flash.h"
//connection
#define LED_PORT GPIOC
#define LED_A (1<<8)
#define LED_C (1<<9)
void SystemCoreClockHSIPLL2(uint32_t RCC_PLLMul_x) {
RCC_DeInit(); //reset rcc
RCC_PLLCmd(DISABLE); //disable PLL
RCC_HSICmd(ENABLE); //enable hsi;
RCC_HCLKConfig(RCC_SYSCLK_Div1); //set sysclk divider
//RCC_PCLK1Config(RCC_HCLK_Div1); //set pclk1/2 dividers
//RCC_PCLK2Config(RCC_HCLK_Div1);
/**
* @brief Configures the PLL clock source and multiplication factor.
* @note This function must be used only when the PLL is disabled.
*
* @param RCC_PLLSource: specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source
* @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
* @arg RCC_PLLSource_HSI48 HSI48 oscillator clock selected as PLL clock source, applicable only for STM32F072 devices
* @arg RCC_PLLSource_HSI: HSI clock selected as PLL clock entry, applicable only for STM32F072 devices
* @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
* PLL source).
*
* @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
* This parameter can be RCC_PLLMul_x where x:[2,16]
*
* @retval None
*/
FLASH_SetLatency(FLASH_Latency_1);
FLASH_PrefetchBufferCmd(ENABLE);
RCC_PLLConfig(RCC_CFGR_PLLSRC_HSI_Div2, RCC_PLLMul_x); //configure pll / divider. _x=[2..16]
RCC_PLLCmd(ENABLE); //enable pll
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) continue; //wait for pll to be ready
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); //set pll as sysclk
while (RCC_GetSYSCLKSource() != RCC_CFGR_SWS_PLL/*0x08*/) continue; //wait for PLL to be ready
SystemCoreClockUpdate(); //update SystemCoreClock
}
//delays some
void delay(uint32_t dly) {
while (dly--) __asm("NOP");
}
int main(void) {
SystemCoreClockHSIPLL2(RCC_PLLMul_12); //go to 48Mhz
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE);
GPIO_InitTypeDef gis;
gis.GPIO_Mode = GPIO_Mode_OUT;
gis.GPIO_OType = GPIO_OType_PP;
gis.GPIO_Pin = LED_A | LED_C;
gis.GPIO_PuPd = GPIO_PuPd_NOPULL;
gis.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(LED_PORT,&gis);
LED_PORT->ODR &= ~(LED_A);
LED_PORT->ODR |= (LED_C);
while(1) {
LED_PORT->ODR ^= (LED_A | LED_C);
delay(1000000);
}
}
If the code works again on your f051-disco, the problem source should be clear.
Also, I read somewhere that current Coocox is buggy. a few versions back and the functions work as expected. You should either try that, or setup your own Eclipse environment with gnu-arm-eabi compilers and STM plug-ins. Then you can use the STM standard peripheral lib in the last version, which should work flawless.
_Or_ you could open an own thread, as this is again and continuesly quite off-topic for STM32 ghetto style and a way more concrete problem with non-ghetto STM
I've read somewhere that some faults pull down the reset line,
LDO | Vout | mAin | mAout | NoLoad µA | mWin | mWout | Eff % |
MCP1700 | 3.283 | 1.89 | 1.88 | 1.3 | 7,37 | 6,17 | 83,71 |
PAM3101 | 3.303 | 1.96 | 1.88 | 57.6 | 7,65 | 6,21 | 81,21 |
MCP1825S | 3.334 | 1.97 | 1.93 | 44.0 | 7,68 | 6,43 | 83,73 |
RT9166 | 3.260 | 1.87 | 1.86 | 6.1 | 7,29 | 6,06 | 83,12 |
simply the ratio of A in versus A out?