Can anyone tell me the speed of just 1 logic gate and the speed of 100 in series?
I have a great project in mind and any advice appreciated, I want the fastest.
Can anyone tell me the speed of just 1 logic gate and the speed of 100 in series?FPGAs don't have logic gates, so I'm not sure what you're asking. Are you talking about input and output buffers on pads?I have a great project in mind and any advice appreciated, I want the fastest.You want the fastest FPGA? I think the 16 nm Virtex 7 is probably going to be the fastest (or at least one of the fastest). It has a minimum pad-to-pad delay of 0.288 nanoseconds in the -3 speed grade (obviously from a high-speed LV diff pair — not sure about standard single-ended pads). Most of these have a GCLK that tops out at about 1 GHz, so that should give you an idea of how "fast" they'll be, given you LUT usage, etc.
When you synthesize and fit your VHDL/Verilog design, you'll be able to get timing reports from your FPGA development software. I'm not smart enough to figure that stuff out on my own, so I just let the tools do the thinking for me.
Maybe you should tell us more about your project?
Just checked out http://www.analog.com/en/products/high-speed-logic/logic-devices/logic-gates.html
That have a range at 45 Gbps. This is good though I don't want to solder 1000's.
Any advice?
Thanks.
the high speed parts was 250MHz maybe even 300MHz
intel Pentium processors are like 3.8G
I wish to develop my own processor using logic gates but as will require 1000+ gates I looked in to chips that contain many, and came across fpga's.
I really need it as fast as possible, you quoted 0.288 ns. Is this typical? Can I use 100's in series per clock cycle or is it 1 logic per cycle?
FPGA's [sic] are programmable logic circuits for And, xor ,nand etc.
May not be an fpga but intel Pentium processors are like 3.8G a second though not sure if that speed is per thread or total threads?
Just checked out http://www.analog.com/en/products/high-speed-logic/logic-devices/logic-gates.html
That have a range at 45 Gbps. This is good though I don't want to solder 1000's. Any advice?
Just checked out http://www.analog.com/en/products/high-speed-logic/logic-devices/logic-gates.html
That have a range at 45 Gbps. This is good though I don't want to solder 1000's.
Any advice?
Thanks.
But FPGAs can easily get to perhaps 500 MHz or more clock frequency, if the FPGA is of a fast enough type and your design is up to it.
I'm about to but a development kit but not sure which one but I'm looking at the MachXO 2280 Breakout Board http://uk.rs-online.com/web/p/programmable-logic-development-kits/7434788/
Can anyone tell me the speed of just 1 logic gate and the speed of 100 in series?
I have a great project in mind and any advice appreciated, I want the fastest.
Thanks
Paul.
If you're new to FPGAs and want to build a microprocessor you can learn a lot from this https://www.dc.uba.ar/materias/disfpga/2010/c2/descargas/TechXclusive%20Creating%20Embedded%20Microcontrollers.pdf Someone has taken the time to re-publish the Xilinx Tech Exclusive articles as a pdf "Creating Embedded Microcontrollers (Programmable State Machines)". It describes the Xilinx Picoblaze 8-bit microcontroller for Spartan3 FPGAs and there is even a version for the newer Spartan6 FPGAs. Be warned, the VHDL for the Picoblaze is a structural descripion using Xilinx primatives and not a behavioral description.
Then there is the Lattice Micro8, very similar to the Picoblaze but with several enhancements, it's also free so you could port it to other vendors silicon like Altera or Xilinx.
Do a bit of background reading and then you will get a better understanding of what FPGAs can and can't do efficiently.
[..]
the above picture is about a very simple 8 bit integer division implemented in fpga.
I can improve the algorithm to get the result in a shorter time but I have to pay more complexity and area, and the best result I can achieve with an integer division of 32bit takes 35 clock cycles.
Not so bad, if we look at commercial ASIC solutions
- 41 clock cycles on AMD K7
- 50 clock cycles on Pentium 4 Netburst
- 29 clock cycles on Intel i7 Haswell
the real difference is
- how many LE does it take? a lot on fpga! ASIC uses less silicon
- which is the maximal frequency you can run the algorithm?
ISE v14.3 says @ 140Mhz on Spartan3E-500
I bought a Digilent ARTY board about a year ago to play with the new tools from Xilinx. It was fairly inexpensive and came with a voucher for the license (really the reason I wanted it).