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Just as an illustration of how 'register' can be used for the Bresenham line drawing algorithm.
I tried it, no improve. The CortexM7 is fast enought, bottleneck is on SDRAM access
I saw in your last post that you were not enabling compiler optimization until recently - unoptimized compiled code is a dead cow.
I do not enable it when I debug. It hides some variables and steps over the code and makes it difficult. When debug is over, I enable it of course.
I actually rewrote some huge parts of the code, corrected some (many) bugs and did some optimisations especially on the global state machine.
I spent a lot of time fixing all thoses bugs, especially in the stop mode, when you shuffle the already captured samples (stored in FPGA DDR3) and change timebase, probe, other stuff.. Everything need to be adapted, trace height, offsets, horizontal placement etc.
All the samples data are now in nanoseconds and millivolts, which abstracts the ADC and samples index to read from FPGA. It helps a lot.
Keeping data integrity between tasks switches, interrupts, DMA accesses and FSYNC of the screen was also no joke.
I also added the sinc interpolation for the lower timebases using CMSIS library. After coutlesses hardfaults, it works like a charm.
However, it doesn't improves that much the trace quality. Gonna have to tries different settings. But with a 10ns sampling period and a 15/20ns rise time on the scope, I doubt I can go any better.
I also finalized the calibration functions, having received a DC power supply which allows the manual calibration to be made.
That cheap power supply is a chinese DC-DC one and is incredibly noisy. It causes troubles for calibrating the smallest calibers. I'm gonna have to build my own voltage references box.
However, I could get a precision up to 0.2% for the well calibrated channels. That's awesome given I use only 234 of the 8 bits of the A/D (margin is kept for input chain errors).
It means, that I can't do any better as theses 0.2% which correspond to half a bit.
The PSU board heats quite a lot, I will have to change the inductors. FPGA also heats seriously. 200MHz everythwere is too high, but atm it's not a priority to rewrite the code for a lower frequency.
On one CPU board (out of two) when I touch the SDRAM the screen flickers.
interesting. Also flickers the first 5 seconds after cold power-up. Probably a poor solder during manufacturing.
How hard is it to get something working 100%...
Now the scope works at 60 FPS almost all the time, even with FFT and 4 traces, with IDLE task still having some time to being.. idle.
It powers-up in less than a second.
That's a banger
i'm gonna have to make a video sometimes.
Seriously thinking about making all this stuff open source when it's mature. Not for free at least given the huge time spent and so the hardware could be produced and bought.
No idea where to start and how to advertise. I'm not good a this.
Gonna need people to test it too.
Hardware must be rock solid, firmware can also be updated!
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Update!
Note: new photos on first page + current specs.
I've been fixing countless bugs, cleaning the code and worked on the hardware.
Found why screen was sometimes flickering: A10 adress was accidentally removed from schematics.
The battery charges, 2 resistors were inverted.
Last version (4) is on the rails earlier than expected.
But it is too much work to go for 1GS/s using HMCAD (1GS/s on 1 channel, 250MS/s on 4 channels) so I made a compromise: 200MS/s on 4 channels.
HMCAD involves switching to Artix-7, redesing of analog stage and I prefer to stabilize current version. Also I don't like that HMCAD interleaves the channels.
Let's call it the 3.1 version, and I may stop here.
Aside correcting some issues I added new functionnalities:
PSU board:
- USB-C charging (using power delivery) replacing barrel connector
- That new USB is also routed to the CPU board for slave connection in addition to the other USB-A (STM32F7 has 2 USB OTG)
- Added battery deep-decharge protection, to disconnect the battery from BQ24610 and system under 3V per cell (reconnects at charger plug)
- Removed the hardware TFT power-on/off supply rail sequencing, will be done by firmware. Too messy by hardware.
- Added monitoring of power supply voltage in addition to battery voltage
- Corrected the TFT backlight enable command
- Remplaced the +5V inductor to dissipate less
- Added a correct battery connector
CPU board:
- Rerouted all analog inputs, high-impedance trace lenght divided by two, all caps and resistors in bottom
- Smallest vias are now 0.3/0.45 instead of 0.2/0.45 (that was a big reroute job) with 2.5H betwwen high-speed traces
- All fast traces around STM32 (SDRAM, LTDC, QSPI..) now respects 2.5H between themseves almost everywhere
- Added a passive 4th order tchebyshev anti-aliasing filter before ADC's
- Added a QPSI FLASH for STM32 (extended storage for code execution or data)
- Improved the trace vertical position schematic using dual feedback amp to prevent loop instability and oscillations
- Improved trig in and trig out traces impedance adaptation and protection
- Added two LDO's for analog supplies to reduce the noise induced by the -3.3V, added mosfets to fast cut/enable analog power when not sampling
- Doubled ADC quantity per channel (thanks to the space freed up by the new routing): now sampling at 200MS/s with a second shifted clock
- Replaced the FPGA from XC7S15 to XC7S25 to get more GPIOs for the new ADC's, also hopping for better timing closure
Note on firmware update:
Architecture will allow to programm both STM32 and FPGA using USB.
I though adding provision for touch screen control. But I have a custom glass, and I don't know how to add capacitive touch function to it.
It looks like all the current capacitive glasses I can found have default dimensions which won't fit in my design.
Will take a break and come back to schematics later.
Created a by me a coffee page. Goal: at least 5$
Here is the global architecture and the routing mess of CPU board!
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This thing continues to impress.
I'm always delighted to see the latest iteration.