Is there anybody willing to share their implementation for 'sawtooth' correction? This has come up several times in this Blog, but never with an example.
19.1 Introduction
u-blox receivers include a time pulse function providing clock pulses with configurable duration
and frequency. The time pulse function can be configured using the UBX-CFG-TP5 message. The
UBX-TIM-TP message provides time information for the next pulse, time source and the
quantization error of the output pin.
This message contains information on the timing of the next pulse at the
TIMEPULSE0 output.
@thinkfat:
The way I understand it from the ublox documentation, the qErr information is available for the next 1PPS pulse.
TDC7200 is quite viable (I've done it myself), but not sensible if you don't implement "sawtooth correction".
TDC7200 is quite viable (I've done it myself), but not sensible if you don't implement "sawtooth correction".Hi Thinkfat, I didn't know the phenomena you have described (and I appreciate it so much).
But why the TDC7200 needs the sawtooth correction and not the Lars solution? I mean, the problem you described seems inherent to any GPSDO, doesn't it?
I have a question about the TDC7200 approach: this device only measures time difference between START events and STOP events, right? Let's suppose that the phase difference has been reduced progressively until 1ns, but at certain time, the second signal comes first (for example the STOP triggers 1ns before), how is this managed? because the TDC72000 does not measure negative phase difference, right?
If we are using a 500kHz as the STOP signal, that would mean the time difference would jump to 1.999us aprox. (1ns-2us). How does the algorithm should manage this?
Thank you again for yor help
But why the TDC7200 needs the sawtooth correction and not the Lars solution?
I mean, the problem you described seems inherent to any GPSDO, doesn't it?
Before you dive in with the TDC7200, there is an even better alternative, the AS6501.
Any (reciprocal) counter needs a very good reference frequency, so I also experimented with variations of the Lars design and also an analog (no cpu) alternative.
See also https://www.eevblog.com/forum/projects/gpsdo-question-378182/
where a 1us Analog TIC is used, without any MCU step at all.
The way I look at it is, if the GPS unit has a 20.833ns granularity, per second, it can resolve/average to 2ns in 10s and 1ns in 20s.
ie a time constant of 20s can make use of a ~1ns TIC.
You rely on the OCXO taking care of stability inside that 20 second average window.
A digital TIC is not mandatory, but if you plan to use a MCU anyway, it does give you extreme number of digits, you can decide how many matter
If you want to work in absolute time (not just GPSDO ), a digital TIC and qErr makes more sense.
Meanwhile, I'm pondering small MCUs with faster timer/capture, as a mid-ground.
Generic MCUs with sysclk timers, are a bit coarse, being the same ballpark (or worse) as the GPS.
Full precision TIC of sub 1ns, are easily able to see a single GPS granularity step, but are probably excessive.
MCUs with Config Logic cells can be used to swallow the XOR Time -> Ramp -> ADC, someone posted a PIC design using Config Logic.
Newer MCUs (STC, Megawin etc) have 150~250MHz capture PLLs, which is quite a bit finer than the GPS, and likely now enough to sense every GPS correction if you want to do that.
The parts are relatively new, which is a minus, but they can offer an entirely digital capture side.
I am not especially interested in using a microcontroller, it's just that the solutions I see over here lead me down that road. I'm trying to implement a GPSDO that is capable to output a disciplined PPS signal, and that has a maximum drift of 1ms over a day or less in holdover mode. So I do not really need a phase difference of picoseconds, but to have a controlled and stable phase difference and, in case the GPS switches off or does not has PVT, the GPSDO can give me a reliable PPS signal to bring to the NTP server (making some temperature compensations if needed).
My first approach was to build basically a PLL with 7 decade counters connected in order to compare two 1PPS signals. Th problem of this approach was that the signal error outputed by the 4046 JK comparator had a very small Duty Cycle (compared to the 1s cycle) and its mean value (introduced into the OCXO) is basically 2,5V (the error signal is uncapable to "move" that value when phase difference is small.
I am not especially interested in using a microcontroller, it's just that the solutions I see over here lead me down that road. I'm trying to implement a GPSDO that is capable to output a disciplined PPS signal, and that has a maximum drift of 1ms over a day or less in holdover mode. So I do not really need a phase difference of picoseconds, but to have a controlled and stable phase difference and, in case the GPS switches off or does not has PVT, the GPSDO can give me a reliable PPS signal to bring to the NTP server (making some temperature compensations if needed).
1ms a day is a little more than 0.1Hz error with a 10MHz signal. That should not be a problem. Most GPSDO will hold the OCXO better than 0.01Hz. It is a matter of choosing a good OCXO and a bit of care with the control voltage, and has very little to do with the quality of the GPS side. My experience is the OCXO is not affected much by temperature, but the control voltage can be (depending on where it comes from). A variation of my design buffers the control voltage in such a way it is derived from a MAX6350 precision 5V source, very little temperature effect.
But why a day of holdover? I have recorded GPSDO output for weeks and not seen any significant outage of the GPS signal. It triggers a reboot if there is a long GPS outage (I think 60 seconds, I'd have to look at the code), and it has never happened. And that is with an antenna in a place with poor reception. The current test has been running 5 days with no signal loss. There are counters in the program to keep stats, up 445492 sec 0 loss.
Very interesting, of course if I can get more than 1 day of holdover I will go for it!!![]()
Did you generated the disciplined PPS from dividing down the 10MHz OCXO freq or did you generated it directly from the controller?
Thank you for the info
The voltage output range of the DAC can be greatly reduced by using only three resistors.
Two to "clamp" the output to the sweet-spot of the OCXO and a third series resistor to reduce the DAC output voltage effect.
So instead of having a DAC where the output ranges from 0..5V, you can create an output that only moves say +/- 100 mV around the sweet-spot over the full 16-bit range.
Of course that's also how you can get to very high gains.
I am about to make a GPSDO based on the design by Lars. I have a query about the 4046 “Tic” circuit.
This version by Murray Greenman differs from the Lars one, plus it has a duplicate pin 10 and just looks wrong with additional grounding (grounding pin 10, an output).
https://www.qsl.net/zl1bpu/PROJ/NGPSDO/TIC.htm
I guess there is nothing much wrong with the Lars version.
Your thoughts are appreciated.
SJ
I am about to make a GPSDO based on the design by Lars. I have a query about the 4046 “Tic” circuit.
This version by Murray Greenman differs from the Lars one, plus it has a duplicate pin 10 and just looks wrong with additional grounding (grounding pin 10, an output).
https://www.qsl.net/zl1bpu/PROJ/NGPSDO/TIC.htm
I guess there is nothing much wrong with the Lars version.
Your thoughts are appreciated.
SJ