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I'm switching a (small, microamps to few milliamps at absolute most) 12V load using a 1.8V logic-level MCU pin. Low power consumption is part of the challenge. The small output current requirements mean I can use a small MOSFET that is capable of being driven directly from an MCU or similar source with relatively low drive capability.
A p-MOSFET directly taking the logic-level signal won't work because the logic high (even if it was 5V) wouldn't be enough to turn the MOSFET off.
There are several approaches I've looked at:
1. Use an off-the-shelf load switch. This is one of the easiest ways, but I spent quite a bit of time going through Digi-Key and reading data sheets and couldn't find a suitable one with low (like under 1 uA) quiescent current. The Diodes AP22850 almost gets there (5 nA typical at 10V), but its max recommended voltage is 11V (12V absolute max).
2. Use an off-the-shelf gate driver. Same problem as above, plus high active current because most gate drivers are designed to switch larger MOSFETs with high gate drive requirements.
3. Make the output open drain (actually, keep it push-pull but add an n-MOSFET to protect the non-12V-tolerant MCU pin, which will also have the effect of inverting it and making it OD), then use a p-MOSFET with a gate pull-up to 12V. Also very simple and good for prototyping, but the issue again is the current draw of the pull-up resistor when the output signal is grounded.
4. Use a 12V-capable comparator as a level shifter. The TI TLV3701 (and others in that family) are the only 12V-capable parts I've found with a supply current rating in the nanoamp range -- 560 nA typical. The downside is it's pretty slow (almost 40 us response time at 50 mV overdrive, 7 us rise time, 9 us fall time). It's still an option, pending further testing to see what current draw is at different switching frequencies.
5. Use a 12V-capable level shifter IC (e.g. Nexperia HEF4104BT, TI CD4504B series, ON MC14504B) to drive a p-MOSFET. This is looking like a good option, if not slightly complex. Two layers of conversion are required (1.8V to 3.3V or 5V, then 3.3V or 5V to 12V) because all of the 12V level shifters are old designs and do not support 1.8V logic. The Nexperia part is the most efficient of the parts I've tested so far, coming in at ~508 nA @ 12V to shift a 1 kHz signal, up to ~16.10 uA to shift a 32.768 kHz signal. However, this ignores any current draw from the 5V supply as I do not have the equipment to measure both at the same time.
6. Use a PNP since the base can safely be left floating to turn it off. The issue with that is the base current.
7. Use a PNP to drive a p-MOSFET. The PNP would only have to drive the MOSFET gate charge current, not the load itself. This would allow the use of a much larger base resistor. However, that introduces the issue of slow rise and fall times. Because of that, it seems like there's a practical higher limit to the PNP base resistor value. The base resistor is usually pretty low (~1k?) in schematics I see around, and looking at Digi-Key for pre-biased BJTs, those max out at 200k (and only a few parts at that; the selection is much wider at 100k).
Building on the last option, here's an approach I thought of. I'm interested in feedback to know if this is crazy or not.
A PNP driving a p-MOSFET basically needs to supply the gate charge, ideally as fast as possible, and then the output voltage needs to be maintained but current draw is just about zero (realistically maybe a few nanoamps in leakage current?). The gate charge is minimal for any MOSFET designed for microamp/single-digit milliamp power levels.
Can a very high base resistor (say 100M, maybe more) safely be used?
If the answer is "yes," that still leaves the issue of rise and fall times. The drive circuit is being controlled by an MCU though, and that provides a lot of flexibility. The obvious approach is to use two MCU pins. Both connect to the base (with a buffer in between to protect the MCU pin from seeing 12V), one with a high (like 100M mentioned above) series resistor and one with a much lower value. The lower-value pin would be pulsed at turn-on time, quickly charging the p-MOSFET gate, after which the high-value pin would keep the PNP on, basically holding the gate at 12V and supplying the p-MOSFET's leakage current.
That's basically tuning the PNP drive circuit for the actual "burst then almost zero" load profile it will see. It seems like a waste to use a low-value resistor with the associated high base current draw if all it's going to be supplying is the leakage current of a MOSFET.
If such a high-value base resistor won't work, here's a related approach:
Use a low-value base resistor and drive the PNP from only one MCU pin. Add a small ceramic capacitor to the p-MOSFET gate, between the gate and ground. When the p-MOSFET gate needs to go high, pulse the PNP -- turn it on for a very short time (potentially a few hundred nanoseconds). The capacitor at the gate would effectively latch the gate at 12V, until the p-MOSFET gets switched on (i.e. grounded) again (or until the capacitor discharges, but that shouldn't be a concern).
The capacitor would need to be sized to be as low value as possible (as it needs to be charged and discharged every time the p-MOSFET gate changes) while high enough that, with leakage currents, it would never drop too low.
The PNP is only on for a very short time at each state change, minimizing the base current draw.
The EFM32's LESENSE peripheral can be (ab)used as a pulse generator to do this.
Thanks! -
You can use a Darlington transistor or make your own out of a pair of transistors, these can have huge gains, the base current can be extremely small. If you want to high side switch you can use a NPN or N channel mosfet to switch a PNP or P channel mosfet.
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Heck, old school BSS138 will get close, and if you need better, RUM001L02 is rated for that.
If you need high side switching, use N into P and some resistors to set gate/base voltage.
Tim -
Why are you looking for a high side switch when the low side NMOSFET can do the job easily?
The BSS138 is a good choice here. Its Vgst is well below 1.8V and with 12V, the leakage should be within 100nA at room temp. -
Thanks all!
This is for that switching regulator project/experiment, so it has to be high side. The 12V feeds an inductor and has to be switched on and off. I've prototyped it out using the N+P with pull-up method, but I'd like to find another solution that doesn't use pull-up (or pull-down) resistors with their associated current draw. AFAIK, any method using MOSFETs is going to require a level-shifted control input; a 1.8V logic high, or even 5V, won't turn a p-MOSFET off if the load is 12V. (At least, I can't find any with a sufficiently high Vgs(th) for that.)
The Darlington transistor is an option I hadn't considered. Can a BJT (whether PNP Darlington or just a single PNP) properly be run with extremely high base resistors, like in the megaohms area, even 100k+? (Provided the load current is small enough and gain high enough, of course.) With such high resistors, would there be a risk of random environmental factors (noise, etc.) causing problems? With sufficiently high current gain it'd be simpler to power the load directly from the BJT rather than using the BJT to level shift the control input and drive a p-MOSFET that powers the load. -
The 12V feeds an inductor and has to be switched on and off.
OK, so switch mode :-). This likely means some tradeoff between gate/base drive power and switching losses, which is fine.
If you need a high side switch, you'll need to use some kind of level shift. A gate drive IC (plus level converters) is at least a good benchmark here. Also, don't some of the EFM32 parts have some 3.3V IO?
If you want to drive a P-Channel FET, you've got three things to do:- Charge the gate at turn on - needs some current
- Hold the gate on - requires very little current
- Turn the gate off - needs some current
I'll think about this. I don't have time to chew on it now, but how about?- Use N-Ch FET off IO pin
- Use a low value 'turn on' resistor in series with a capacitor to deliver turn on current pulse
- Use a high value 'keep on' resistor
- Use some kind of steering diode and turn-off transistor to bring Vds to zero once gate removed (some thinking required to make sure this doesn't burn too much power during 'keep on' phase)
An outside the box solution - may be totally inappropriate! - how about using an N-Ch MOSFET on the high side and a gate drive transformer? Gate drive transformer can be driven from 1.8V supply rail using some high output drive logic buffer ICs. Probably no go at 1kHz, though.
We may have a bit of an XY situation going on, so I'm going to ask some questions:- What is the expected duty cycle of this high side switch? If the duty cycle is low, maybe the gate drive losses aren't actually very big.
- Can you flip the eventual load to be referenced to the positive supply and flip your switch mode topology 'the other way up' to achieve a low side switch?
- Can you change your switch mode topology to something with a low side switch and the output how you want it (e.g. flyback, SEPIC)?
- Can you change the switch mode design to provide some useful behaviour, such as always turning on at zero current (which removes turn on losses and means we can switch FET on slowly) or resonating to provide zero current at turn off (which removes turn off losses and means we can switch FET off slowly)?
- Given the tradeoff between gate drive and main switch losses, it will probably be best to select a small P-Ch FET with moderately high on resistance and as little gate charge as possible
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You can easily calculate the base current needed for a given BJT by looking up the gain and knowing how much current you need it to switch, then use Ohms law to calculate the required base resistor. For example a Darlington transistor may have a gain of around 1,000, so if you wanted it to control 1A you'd need to provide roughly 1mA of base current.
You could also use a NPN BJT to control a P channel mosfet, you'll need a pullup on the gate but it could be >1M provided the RC time constant with the gate capacitance will result in an acceptable turn-off time. The higher value pullup you use on the gate the less current you will pull while the transistor is on, but the slower the mosfet will turn off. The NPN in this case would only be passing current to pull the gate down so the base current can be very small. -
How fast?
Also, do you really need to run it from an MCU? You're wasting way more effort, and power, in the MCU than an off the shelf regulator. Remember that you need to also run an analog comparator and/or fast ADC to implement a reliable SMPS, and those will take 100s uA from what I've seen among MCUs.
1.8V does have the interesting opportunity to run a BJT at high efficiency. You could use a couple BJTs as level shift to a bootstrapped NPN. LT makes a lot of bipolar regulators that do this; the bootstrap supplied NPN means they work down to surprisingly low e.g. 2-3V inputs. (Thanks to other tweaks, they retain good efficiency at higher voltages, too; those wouldn't be feasible in a discrete circuit here.)
If you really only need a few mA output, have you considered a charge pump instead? Don't forego LDOs either, they can offer much lower Iq than your MCU will use. That alone can be well worth the lost power.
Tim -
I'm building the buck converter from scratch for fun/learning and also because most off-the-shelf parts (except LTC3388) have very low efficiency at low loads. The 12V input is the issue -- there are off-the-shelf LDOs and buck converters with IQ under 100 nA if the input is maximum 5V or so. There's not any critical need for high efficiency (it's wall-powered); I'm using this as an exercise in low-power design. The fact that it's more complex than just using an off-the-shelf IC is actually a benefit there.
If you need a high side switch, you'll need to use some kind of level shift. A gate drive IC (plus level converters) is at least a good benchmark here. Also, don't some of the EFM32 parts have some 3.3V IO?
These EFM32TG11 parts actually have some 5V-tolerant IOs, but I'm not sure how that would be useful here. They won't output more than IOVDD (max 3.8V).
The low load should mean that a full gate driver isn't really necessary, since I can use small MOSFETs. It's just the level shifting part of it that poses the issue -- can't turn off a P-MOSFET with 12V source without something pretty close to 12V.If you want to drive a P-Channel FET, you've got three things to do:
- Charge the gate at turn on - needs some current
- Hold the gate on - requires very little current
- Turn the gate off - needs some current
I'll think about this. I don't have time to chew on it now, but how about?- Use N-Ch FET off IO pin
- Use a low value 'turn on' resistor in series with a capacitor to deliver turn on current pulse
- Use a high value 'keep on' resistor
- Use some kind of steering diode and turn-off transistor to bring Vds to zero once gate removed (some thinking required to make sure this doesn't burn too much power during 'keep on' phase)
Yep -- I had the thought of doing something similar with two GPIO pins to deliver a turn-on/off pulse and a continuous keep-on current. That's still an option, but the power draw will need to be weighed against just using a few off-the-shelf level shifters (one 1.8V to 5V using a charge pump supply, then 5V to 12V). One consideration is that the MCU is going to be in EM2 sleep with only a 32.768k clock running, so any short pulsing will incur the startup delay of the high-frequency oscillator. (The LESENSE peripheral will run off the low-frequency clock and automatically start and stop a high-frequency oscillator for just the pulse period. This minimizes the time the high-frequency oscillator is on, trading off startup latency for power savings.) The power cost and latency of that might make the off-the-shelf shifters the best option.An outside the box solution - may be totally inappropriate! - how about using an N-Ch MOSFET on the high side and a gate drive transformer? Gate drive transformer can be driven from 1.8V supply rail using some high output drive logic buffer ICs. Probably no go at 1kHz, though.
An option I never knew of. While the frequency will probably hit 1 kHz or higher, I'm going to do more research on this one. Thanks!We may have a bit of an XY situation going on, so I'm going to ask some questions:
- What is the expected duty cycle of this high side switch? If the duty cycle is low, maybe the gate drive losses aren't actually very big.
(Also responding to Tim's similar question.)
Using a PFM control mode where the comparator switches on and off a 32.768 kHz clock to maintain regulation, I think that would be the maximum. It's a clock, so 50% duty cycle. (Technically since the comparator is asynchronous, I suppose it could switch multiple times within the same high cycle, but that seems unlikely assuming the use of comparator hysteresis and suitably-sized passives.)
Using a fully hysteretic control mode where the clock isn't used at all, just switching 12V on and off based on the comparator output, I'm not sure how to define the same parameter, but I'm comfortable calling the above an absolute max. I'll size the passive parts to ensure it.
The issue with gate driver and load switch ICs I looked at is the quiescent current in the off state.
I look at turn-on and turn-off times not because there are any critical requirements there, but rather just as a metric to compare. I assume faster is likely to lead to better regulation (comparator switches state and the faster power can be turned on or off, the closer the output will be to the intended voltage).- Can you flip the eventual load to be referenced to the positive supply and flip your switch mode topology 'the other way up' to achieve a low side switch?
I'm not sure, but I think I see what you're suggesting and that seems like a very clever idea. I'll try to sketch it out.- Can you change your switch mode topology to something with a low side switch and the output how you want it (e.g. flyback, SEPIC)?
I will look into both topologies.- Can you change the switch mode design to provide some useful behaviour, such as always turning on at zero current (which removes turn on losses and means we can switch FET on slowly) or resonating to provide zero current at turn off (which removes turn off losses and means we can switch FET off slowly)?
I'm not sure I follow. Wouldn't that mess with regulation (keep the switch on too long and the output voltage will be higher than intended?)- Given the tradeoff between gate drive and main switch losses, it will probably be best to select a small P-Ch FET with moderately high on resistance and as little gate charge as possible
Agreed. That's also what Linear did in the LTC3388, which is the only off-the-shelf part I know of in this area. (Linear solves the problem here by generating an internal rail at 4.8V below Vin for high-side switching. I suspect this is something that can only be done efficiently in an IC, where they presumably can also tune the Vgs(th) of the integrated power MOSFET.)You can easily calculate the base current needed for a given BJT by looking up the gain and knowing how much current you need it to switch, then use Ohms law to calculate the required base resistor. For example a Darlington transistor may have a gain of around 1,000, so if you wanted it to control 1A you'd need to provide roughly 1mA of base current.
Yes, but if I calculate (from data sheet specs) that a given BJT would need, say, 500 nA base current to switch this load, can I actually use a resistor that high (for that example, 24M at 12V) or is there some other consideration that will prevent it from working consistently? Sort of like how pull-up resistors on open drain signals theoretically could be 1M, but at the cost of robustness (picking up noise that switches the input erroneously).
Normally I use MOSFETs for anything like this because I find them way easier to reason about and more efficient for my uses. The only reason I'm looking at BJTs here is because the base can safely be left floating to turn them off, from what I understand, instead of needing a ~12V signal like a p-MOSFET would. (The advantage of current control for this scenario, in other words.)Also, do you really need to run it from an MCU? You're wasting way more effort, and power, in the MCU than an off the shelf regulator. Remember that you need to also run an analog comparator and/or fast ADC to implement a reliable SMPS, and those will take 100s uA from what I've seen among MCUs.
The MCU would already be present for other purposes, so adding the regulation functionality to it has minimal add-on current. The EFM32 parts (EFM32TG11 - Tiny Gecko S1 is what I'm playing with now, but this applies to all of them) have ultra-low-power configurable comparators. For this part, the data sheet claims 50 nA typical for 30 us delay and 306 nA for 3.7 us (both 100 mV overdrive). Other parts with low-power comparators are the Atmel SAM L series (L10 and L21 are actually slightly better in power/delay than EFM32, IIRC) and the STM32Lx parts.
If the MCU wasn't already present and usable for this purpose, I'd be looking at one of the nanopower comparators. The Maxim MAX9645 (and family) is a good one suggested by Marco with a built-in 0.2V reference. There are also a few parts around or under 300 nA without references from TI and ST.
For a low-power crude reference (if using a part without an integrated one), I think I can use the TI TPS7A02 LDO powered by a voltage doubler charge pump. IQ on that is rated at 25 nA typical. Another idea I had was to use a proper reference voltage IC (all of which have relatively high power requirements) but pulse it every X seconds to charge a capacitor. The only draw from the capacitor would be the input bias current of the comparator and other leakage, so I think this *should* work with a suitably-sized capacitor and startup frequency/time.1.8V does have the interesting opportunity to run a BJT at high efficiency. You could use a couple BJTs as level shift to a bootstrapped NPN. LT makes a lot of bipolar regulators that do this; the bootstrap supplied NPN means they work down to surprisingly low e.g. 2-3V inputs. (Thanks to other tweaks, they retain good efficiency at higher voltages, too; those wouldn't be feasible in a discrete circuit here.)
Is this one such part you're referring to? Just want to check because Linear tends to have good technical descriptions in their data sheets so I can research this further.If you really only need a few mA output, have you considered a charge pump instead? Don't forego LDOs either, they can offer much lower Iq than your MCU will use. That alone can be well worth the lost power.
Yes, but I didn't see a 12V input-capable one with very high ultra-low-load efficiency. I think that's because there's no real market for this kind of power optimization in 12V parts and thus no reason for semiconductor companies to invest R&D money in it. For ~5V, on the other hand, there's a huge market in portable devices and so TI and others have designed parts with incredibly low IQ (and thus high efficiency at low load), e.g. TPS7A02 LDO and TPS62840 buck (60 nA IQ). -
I'm building the buck converter from scratch for fun/learning and also because most off-the-shelf parts (except LTC3388) have very low efficiency at low loads.
Ah, okay. You will be well served to understand SMPS in the first place (it's not clear what your knowledge level is here), and then to optimize them for efficiency. A good lesson might be more of the methodology to optimize things. Measure subcircuits and see where the dominant losses are, and figure out ways to improve them locally. Then take a step back and see if you can swap around the functionality of those circuits, replacing whole sets with lower consumption types. Then repeat local optimization, etc.
A few years ago I did this exercise,
A switch and resettable fuse, with a bidirectional current limiting function.
For supply voltages up to 30V and currents up to 20A (selectable in 5A steps), this device will limit the current flow accordingly. The voltage drop is dissipated onboard, though it can be "recycled" through a ground pin, in which case it acts like a current-limiting buck converter.
This gives a sharper current limit than a dumb resistor, lower on-state losses, and a fast, no-wear fuse action.
It also has remote start/stop connections (via optoisolators), a one-shot timer (the fuse "blows" after 150ms), and thermal protection.
You can reset the "fuse" about ten times in a row, before temperature rises too high and the limit pulls in. Once it cools down a bit, you can continue to reset it.
One downside is, the onboard filter capacitors still draw some inrush current, and the filter inductor adds series inductance. Neither is a problem in the intended application -- switching loads with relatively large capacitances.
It's powered by a 9V battery, and boasts about a month continuous on time. I can't do that with regular off-the-shelf gate drivers, for instance: they all take upwards of 0.2mA Iq, as much as this circuit uses in total. And that leaves nothing for the current comparator, temperature sensor and UVLO. (On the upside, most do integrate UVLO.)
So the circuit is discrete, mostly BJTs, power MOSFETs of course, and a CD4000 gate.
The sense/drive circuit switches at up to 200kHz, with rise/fall time of 300ns or so, not terribly efficient but that fortunately doesn't matter in a device which is almost all loss anyway.
It actually consumes less power while active, as it steals some switching loss to power itself.
A purpose-made IC can absolutely beat the pants off this thing, easily 5x lower Iq I would expect. But no one makes one for this exact function, nor enough building blocks (comparators, logic, etc.) with adequate speed-accuracy-Iq tradeoff. So there's not much alternative.
And just a reminder that this is in fact a 600W power converter -- just not a terrifically purposeful one (it makes heat), nor for continuous operation. So, doing all that with good battery life, isn't too bad.QuoteYep -- I had the thought of doing something similar with two GPIO pins to deliver a turn-on/off pulse and a continuous keep-on current. That's still an option, but the power draw will need to be weighed against just using a few off-the-shelf level shifters (one 1.8V to 5V using a charge pump supply, then 5V to 12V).
There are better ways. They'll always take more parts, of course. Balanced configurations help a lot. You can have a circuit where transition current draw is relatively large, but quiescent current is low. This can be done at low current to begin with, and then sharpened with later stages (say, a CMOS gate). You can use a complementary emitter follower to drive larger MOSFET gates while wasting almost no current (the downside is 0.6V saturation to either rail; this makes logic-level FETs unattractive, but with a 12V supply, that's still perfectly fine).
For example, make a high-side "bus hold" latch: two CMOS inverters in a loop, with a resistor in series with each output so one or the other can be overdriven by a stronger load. Switch these with low side NMOS, driven from the MCU, complementary. There's your level shift, and it doesn't consume any Iq. Only 12V / R_series is drawn during switching, which can be say 100ns long. (The limiting factor is actually not so much the resistance, but the total charge of the opposite side gate's input capacitance plus the drain capacitance of the other NMOS. This can be some 10s of pF, which isn't terrible.)
Then boost up the output with a few inverters in parallel (this is fine using e.g. CD4069s, but be mindful when connecting Schmitt trigger gates in parallel (e.g. 74HC14), as their delays may not match, drawing extra shoot-through current), and drive whatever power transistor you need.
If you use NPNs instead of NMOS on the low side, you can add an emitter resistor, limiting the pull current; as long as R_series * Ic is enough to flip the "bus hold" latch state, it works. The difference is, this is true regardless of what the local ground voltage is: you could use 74HC14 or '04 here, and a bootstrap 3-5V supply, to drive an NMOS switch. (You wouldn't want to use strong NMOS to pull on a bootstrapped driver, because they'll want to pull it all the way to GND. Yes, you can add source degeneration all the same, it's just harder to calculate because Vgs(on) is higher and less consistent.) The bootstrap in turn might be supplied from a charge pump doubler from the 1.8V supply (or maybe you have 3-5V handy elsewhere, I don't know).
BTW, PMOS performs about 2.5 times worse than NMOS, so there is a real advantage, saving on Qg * Fsw current draw. Likewise, prefer a relatively small transistor (higher Rds(on), lower Qg(tot)), since conduction losses won't be your biggest problem here.
That's even an error that a lot of people make, even if they don't care about drive power: they see 4mΩ or whatever in the headline, and are sold on that. What could be better, right? Nevermind that the drain is 10nF at low bias, or the gate is 200nC. And then they get socked with all these losses, and their interaction with stray inductances, and the whole thing keeps blowing up...
There are also worse ways, that can still be alright in special cases. For example, a charge pump or DC restore circuit. You have a 1.8V swing on an MCU pin; capacitor-couple that to the high side, with a resistor bleeding off charge so it idles at +12V. Use something like RZM001P02, that only needs 1.8V drive. The catch: the 12V supply must not vary more than a fraction of a volt, or the cap will dutifully turn on (or erroneously turn off) the transistor. This makes startup and transient cases a bitch.QuoteYes, but if I calculate (from data sheet specs) that a given BJT would need, say, 500 nA base current to switch this load, can I actually use a resistor that high (for that example, 24M at 12V) or is there some other consideration that will prevent it from working consistently? Sort of like how pull-up resistors on open drain signals theoretically could be 1M, but at the cost of robustness (picking up noise that switches the input erroneously).
Note that BJTs are just as voltage-controlled as MOSFETs, so you still need to charge and discharge that base voltage. It's a lot less charge than a FET of the same dimensions, but you're at a disadvantage because you're doing it from 12V away. In short, 24M gives a long time constant (10s µs, if that?).
Typical solution is a B-E resistor to aid turn-off. (This also keeps collector leakage somewhat lower. Roughly speaking, C-B leakage flows into the base and gets multiplied by hFE. This is also roughly why Vcbo > Vceo: the leakage current contributes to a lower breakdown voltage.)QuoteIs this one such part you're referring to? Just want to check because Linear tends to have good technical descriptions in their data sheets so I can research this further.
Like this, used one a bunch of years ago, still have the number handy:
https://www.analog.com/media/en/technical-documentation/data-sheets/3481fc.pdf
Note the switch voltage drop is a fraction of what LT1074/6 does, because of the bootstrap. All the '74/6 can do is pull the base up to VCC, and the emitter hangs down by 0.7V or so per transistor. Supply goes down to 3.something V, whereas discrete MOSFETs aren't much use below 5-8V.
There are some old chips working in such a domain, https://datasheets.maximintegrated.com/en/ds/MAX631-MAX633.pdf for example. (They're still available, amazingly enough, but are priced like an old boutique part. Not that they're exactly relevant, being boost type.) Voltage rating suggests metal-gate CMOS (ala CD4000, 74C00 family).
Note that the block diagram is much more than a comparator and driver, and these are still pretty basic devices.
At low currents, you'll probably be fine with hysteretic or PFM (or "pulse skipping") operation, but the peak current (and preferably the average as well) needs to be monitored to ensure safe operation.
You can use a few-us comparator, but that delay needs to be a small fraction of the total cycle, so you'll be in the low 10s kHz doing it that way, and you need big inductors. This isn't a very cost-effective approach. But yeah, you can certainly develop an understanding this way.QuoteYes, but I didn't see a 12V input-capable one with very high ultra-low-load efficiency. I think that's because there's no real market for this kind of power optimization in 12V parts and thus no reason for semiconductor companies to invest R&D money in it. For ~5V, on the other hand, there's a huge market in portable devices and so TI and others have designed parts with incredibly low IQ (and thus high efficiency at low load), e.g. TPS7A02 LDO and TPS62840 buck (60 nA IQ).
A lot of regulators (of ordinary ratings, e.g. 30V input) boast low Iq, though it varies whether it's in shutdown or idle conditions. Can always wrap a hysteresis comparator around one, forcing burst-mode output while maintaining reasonable efficiency. Note that the comparator only needs to respond to voltage changes, i.e., 10s or even 100s of µs. The downside is a lot of output voltage ripple, but that's just going to happen in this domain, and again, you can LDO it, taking off only a fraction of a volt this time, to clean it up.
Tim -
Thanks for such a long and detailed response!
Ah, okay. You will be well served to understand SMPS in the first place (it's not clear what your knowledge level is here), and then to optimize them for efficiency.
I'd say just a very basic level of understanding so far. Enough to get a crude prototype working, but very, very, very far from what professionals like you or the engineers at TI, AD/LTC, etc. can do. My background is in software, only recently getting into hardware development. I happen to like optimization and working close to the metal, even in cases where it's not commercially viable, and abhor the "we've got 10 layers of virtualization + 100 more layers of abstraction but we'll just throw more hardware at it if it's too slow" mentality.A good lesson might be more of the methodology to optimize things. Measure subcircuits and see where the dominant losses are, and figure out ways to improve them locally. Then take a step back and see if you can swap around the functionality of those circuits, replacing whole sets with lower consumption types. Then repeat local optimization, etc.
Agreed. In a way that's what I've been doing here by focusing on the power stage, as I know that with the simplest pull-up approach it's going to be a sizable-enough source of loss.A few years ago I did this exercise,
...
A purpose-made IC can absolutely beat the pants off this thing, easily 5x lower Iq I would expect. But no one makes one for this exact function, nor enough building blocks (comparators, logic, etc.) with adequate speed-accuracy-Iq tradeoff. So there's not much alternative.
That's a cool project! I eventually want to work on adding overcurrent protection to this as well (just as a safeguard to ensure an accidental short -- or hardware failure causing one -- doesn't result in smoke).For example, make a high-side "bus hold" latch: two CMOS inverters in a loop, with a resistor in series with each output so one or the other can be overdriven by a stronger load. Switch these with low side NMOS, driven from the MCU, complementary. There's your level shift, and it doesn't consume any Iq. Only 12V / R_series is drawn during switching, which can be say 100ns long. (The limiting factor is actually not so much the resistance, but the total charge of the opposite side gate's input capacitance plus the drain capacitance of the other NMOS. This can be some 10s of pF, which isn't terrible.)
Hmm, I don't completely understand. I get the concept of a bus-hold latch and get that CMOS inverters can be used to produce a 12V output from an MCU's logic low output, but how would the CMOS inverter ever be made to produce a logic low output without a 12V (or close to that -- whatever the logic high threshold is with a 12V Vcc) input?
I suppose a CMOS inverter could theoretically be used as a sort of level shifter by using the MCU pin (with NMOS in between) to low-side switch (i.e. ground or hi-Z) the inverter's ground and input pins, but I don't see how that's really any different from just driving a PMOS directly and floating the gate (which, as I understand, is not a robust solution).BTW, PMOS performs about 2.5 times worse than NMOS, so there is a real advantage, saving on Qg * Fsw current draw. Likewise, prefer a relatively small transistor (higher Rds(on), lower Qg(tot)), since conduction losses won't be your biggest problem here.
That's even an error that a lot of people make, even if they don't care about drive power: they see 4mΩ or whatever in the headline, and are sold on that. What could be better, right? Nevermind that the drain is 10nF at low bias, or the gate is 200nC. And then they get socked with all these losses, and their interaction with stray inductances, and the whole thing keeps blowing up...
I'm glad to know I've been doing MOSFET shopping at least somewhat properly.
Total gate charge is one of the metrics I sort by.There are also worse ways, that can still be alright in special cases. For example, a charge pump or DC restore circuit. You have a 1.8V swing on an MCU pin; capacitor-couple that to the high side, with a resistor bleeding off charge so it idles at +12V. Use something like RZM001P02, that only needs 1.8V drive. The catch: the 12V supply must not vary more than a fraction of a volt, or the cap will dutifully turn on (or erroneously turn off) the transistor. This makes startup and transient cases a bitch.
Speaking of that, one approach I considered was to use a voltage-doubling charge pump with multiple stages to increase the 1.8V supply to something over 12V to drive the MOSFET. That felt like a hack though -- boosting the 1.8V supply to 12V when there's already a 12V supply there, just because the boost can easily be switched from a 1.8V MCU pin. The upside is that it would allow me to get a voltage over 12V and use an NMOS. Maybe that kind of approach is still worth looking at further, even if it does feel like a hack?
The charge pump design I had in mind was (EEVblog #473). I was also able to quickly prototype that on a breadboard using my AD2 (which is really nice because it bundles a scope, DC power supply, pattern generator, logic analyzer, and some other tools).QuoteYes, but if I calculate (from data sheet specs) that a given BJT would need, say, 500 nA base current to switch this load, can I actually use a resistor that high (for that example, 24M at 12V) or is there some other consideration that will prevent it from working consistently? Sort of like how pull-up resistors on open drain signals theoretically could be 1M, but at the cost of robustness (picking up noise that switches the input erroneously).
Note that BJTs are just as voltage-controlled as MOSFETs, so you still need to charge and discharge that base voltage. It's a lot less charge than a FET of the same dimensions, but you're at a disadvantage because you're doing it from 12V away. In short, 24M gives a long time constant (10s µs, if that?).
Typical solution is a B-E resistor to aid turn-off. (This also keeps collector leakage somewhat lower. Roughly speaking, C-B leakage flows into the base and gets multiplied by hFE. This is also roughly why Vcbo > Vceo: the leakage current contributes to a lower breakdown voltage.)
I had a feeling there was some practical reason such a high base resistor wouldn't work on its own. Thanks for confirming!QuoteIs this one such part you're referring to? Just want to check because Linear tends to have good technical descriptions in their data sheets so I can research this further.
Like this, used one a bunch of years ago, still have the number handy:
https://www.analog.com/media/en/technical-documentation/data-sheets/3481fc.pdf
Note the switch voltage drop is a fraction of what LT1074/6 does, because of the bootstrap. All the '74/6 can do is pull the base up to VCC, and the emitter hangs down by 0.7V or so per transistor. Supply goes down to 3.something V, whereas discrete MOSFETs aren't much use below 5-8V.
There are some old chips working in such a domain, https://datasheets.maximintegrated.com/en/ds/MAX631-MAX633.pdf for example. (They're still available, amazingly enough, but are priced like an old boutique part. Not that they're exactly relevant, being boost type.) Voltage rating suggests metal-gate CMOS (ala CD4000, 74C00 family).
Note that the block diagram is much more than a comparator and driver, and these are still pretty basic devices.
Thanks! I'll read through the data sheets and also look for other documents (app notes, etc.) that might be useful.At low currents, you'll probably be fine with hysteretic or PFM (or "pulse skipping") operation, but the peak current (and preferably the average as well) needs to be monitored to ensure safe operation.
Is the current monitoring just for short circuit protection?You can use a few-us comparator, but that delay needs to be a small fraction of the total cycle, so you'll be in the low 10s kHz doing it that way, and you need big inductors. This isn't a very cost-effective approach. But yeah, you can certainly develop an understanding this way.
Hmm. The Atmel SAM L10 and L21 chips seem to have incredibly good comparator specs, far better than any comparator IC or other MCU comparator I can find (including EFM32). Take a look at page 1029 (using the page numbers in the footer) of the L21 data sheet.
They're claiming 560 ns typical, 1.41 us max at 289 nA typical, 2.2 uA max; or 330 ns typical, 2.7 us max at 549 nA typical, 2.495 uA max. Those are all +/- 100 mV overdrive.
The L10 claims similarly impressive specs.
Are these realistic or too good to be true? Heck, I'm pretty sure I've read a comment from you in some other thread saying Atmel's analog design process is poor, which just further makes me question how realistic their best-in-class numbers are.
How big of an inductor are you talking? I noticed the LTC3388 requires 22 uH minimum and has recommendations up to 100 uH, which is on the bigger side of any regulator ICs I've looked at.A lot of regulators (of ordinary ratings, e.g. 30V input) boast low Iq, though it varies whether it's in shutdown or idle conditions. Can always wrap a hysteresis comparator around one, forcing burst-mode output while maintaining reasonable efficiency. Note that the comparator only needs to respond to voltage changes, i.e., 10s or even 100s of µs. The downside is a lot of output voltage ripple, but that's just going to happen in this domain, and again, you can LDO it, taking off only a fraction of a volt this time, to clean it up.
They do, but there are a lot of varying definitions of "low IQ" seemingly based on the product they're trying to sell. I've not seen any (other than LTC3388) where the IQ would not be a significant efficiency hit at, say, 100 uA load current. -
Hmm, I don't completely understand. I get the concept of a bus-hold latch and get that CMOS inverters can be used to produce a 12V output from an MCU's logic low output, but how would the CMOS inverter ever be made to produce a logic low output without a 12V (or close to that -- whatever the logic high threshold is with a 12V Vcc) input?
Use an NMOS (driven by MCU pin) to tug one or the other input low.
So one inverter output connects to a resistor, which connects to the other inverter input. NMOS drain to input, source to GND, gate to MCU. Double it, with the inverters in a ring. MCU outputs alternately pulse high to change state. It's a somewhat crude implementation of an RS flip-flop.QuoteIs the current monitoring just for short circuit protection?
It can be used for dynamics as well. The key fact is this: a switched-inductor, voltage source converter, acts as an integrator.
In the same way that you don't know the instantaneous value of an accumulator (i.e., a = a + x) until you read it, you don't know what current is in the inductor until you measure it. In software, the hazard might be overflow (a pretty bad defect in a DSP path), but IRL, the hazard is releasing magic smoke.
At low power, you're very likely going to be in DCM, where you can make some assumptions. If the inductor current is definitely going to zero every cycle, well, the accumulator resets, so you don't have to worry about that.
But therein lies the problem: if your assumption ever gets broken, so does your circuit. Short circuit is a typical case, yes, but you don't want to neglect startup or load transients, either!
It's easy to get the mean case right; it's all about the edge cases. You can program almost entirely by feeling out the edges of a problem, or an algorithm, with little or no need to worry about the average case. Same here.
Not that it's a huge problem even then, since you could just use oversized (or undersized, for that matter) transistors, or an inductor with relatively high resistance, etc. These all have impacts on cost, size* or efficiency, of course.
*Not that you can actually get a minimal sized transistor: RF MOSFETs are pretty much gone nowadays, so there's not much chance of using a 10mA 20V part unless you want to go digging through old stock. And RF types have never been the cheapest, even though they have the smallest active area. So, this particular economy only applies to monolithic design, if at all; go figure!QuoteHmm. The Atmel SAM L10 and L21 chips seem to have incredibly good comparator specs, far better than any comparator IC or other MCU comparator I can find (including EFM32). Take a look at page 1029 (using the page numbers in the footer) of the L21 data sheet.
They're claiming 560 ns typical, 1.41 us max at 289 nA typical, 2.2 uA max; or 330 ns typical, 2.7 us max at 549 nA typical, 2.495 uA max. Those are all +/- 100 mV overdrive.
Dunno. 100mV is a lot of overdrive (you might use up all of that in a shunt resistor just on base level alone -- there are a lot of switching controllers out there that use a 50-200mV range current sense signal), but sub-1uA is awfully optimistic, even so.
I wonder if it's possible by implementing the function in fine pitch circuitry (<= 100nm scale?). My understanding is analog performance drops off below 250nm or so, which should be performance in terms of bandwidth at power and efficiency, which will be relevant to the performance of something like a comparator. And that's around the scale of most CMOS, so no one should be doing anything terribly remarkable.
Could also be that they're always very hesitant to give any kind of confidence behind power consumption numbers. Rightfully so, as it depends completely on code. But this should be simple enough not to make an orders-of-magnitude underestimate.QuoteAre these realistic or too good to be true? Heck, I'm pretty sure I've read a comment from you in some other thread saying Atmel's analog design process is poor, which just further makes me question how realistic their best-in-class numbers are.
Atmel is a big company, with a lot of products, designed by a lot of people, over a long time. That comment was about classic ATMEGA parts, which I heard from someone else (I haven't tested it myself, mind; other than the ADC and REF specs, which are right there in the datasheet). I haven't heard anything about the other families (XMEGAs, newer MEGAs, SAMs, etc.).
TI for example has their share of lemons, both in parts and documentation. Even ADI has made a few boners (most notably: a 24-bit ADC with "SPI" interface, that doesn't reset clock state when CS is deasserted; if it ever misses a SCK edge, or receives an extra glitch, all data until the end of time will be gibberish; the only cure is a power cycle!). It would be unfair to judge a large, heterogeneous organization by just one of its parts, so there's not much you can generalize from these, just gotta keep testing parts and getting familiar with them.QuoteHow big of an inductor are you talking? I noticed the LTC3388 requires 22 uH minimum and has recommendations up to 100 uH, which is on the bigger side of any regulator ICs I've looked at.
If you plugged in numbers like: 12V in, 5V 10mA out, 20kHz, into a calculator, you'd get something like 8mH for BCM. And proportionally more for proportionally lower currents, of course.
That's not so terrible (small, 10s mH inductors are certainly available), but inductances that large are I think hard to find with low losses and small sizes. Q is roughly proportional to sqrt(F), so the low frequency just keeps killing Q (and thus efficiency), and the small size doesn't help. The frequency of peak Q tracks with the linear size of the part, more or less, so a small part is extra disadvantaged at low frequencies.
Smaller inductances imply higher dI/dt, implying faster comparators to avoid fault conditions.
Tim -
Can't you just use a standard CMOS logic level shifter circuit to drive the P-MOSFET?
MP1, MN2, MP2 and MN3 can be replaced with low voltage CMOS inverter gates, such as the 74LVC2G04. MN1 & MN4 can be the BS138 and MP3 & MP4, the BSS84.
https://wiki.analog.com/university/courses/electronics/electronics-lab-voltage-level-shifter
http://www.ti.com/lit/ds/symlink/sn74lvc2g04.pdf
http://www.farnell.com/datasheets/2298371.pdf
https://www.onsemi.com/pub/Collateral/BSS138-D.PDF
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I wonder if flyback would be feasible (not sure how bad transformer losses are compare to a single inductor). This can be made with low side switching and everyone is happy.
As for small general purpose MOSFETs, anything with AK suffix from NXP (NX3020AK, NX7002AK, BSS138/84AK), CSD15380F3 (
), FDV301N, some SSM3xxxx from Toshiba...
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Use an NMOS (driven by MCU pin) to tug one or the other input low.
So one inverter output connects to a resistor, which connects to the other inverter input. NMOS drain to input, source to GND, gate to MCU. Double it, with the inverters in a ring. MCU outputs alternately pulse high to change state. It's a somewhat crude implementation of an RS flip-flop.
Ah, I think I have an idea now of how this is supposed to work. I'll simulate it.QuoteIs the current monitoring just for short circuit protection?
It can be used for dynamics as well. The key fact is this: a switched-inductor, voltage source converter, acts as an integrator.
In the same way that you don't know the instantaneous value of an accumulator (i.e., a = a + x) until you read it, you don't know what current is in the inductor until you measure it. In software, the hazard might be overflow (a pretty bad defect in a DSP path), but IRL, the hazard is releasing magic smoke.
At low power, you're very likely going to be in DCM, where you can make some assumptions. If the inductor current is definitely going to zero every cycle, well, the accumulator resets, so you don't have to worry about that.
But therein lies the problem: if your assumption ever gets broken, so does your circuit. Short circuit is a typical case, yes, but you don't want to neglect startup or load transients, either!
So this, if I understand correctly, is about making sure the inductor isn't overcharged beyond its rated current limit (or it becomes a fire hazard).
Even if the load current and inductor size were such that it was not operating in DCM, does hysteretic control not effectively take care of this? The comparator isn't going to trip until the output voltage drops below a certain point, which presumably means there's not some abundance of current stored in the inductor.
There's a need to make sure the peak load current isn't higher than what the circuit can support, of course (whether that's a short or someone trying to power a high-end Nvidia card off a micropower supply).
This does make me question whether there's something basic in "buck converters 101" that I'm missing. The LTC3388 data sheet mentions ramping up the inductor current to 150 mA and then down to 0 mA, as if they're doing some kind of current monitoring similar to what you mention. (The LTC3388 uses hysteretic control.) The part I don't get is how they can do some kind of current control like this without affecting output voltage regulation. Surely if they keep the PMOS on until the inductor current reaches 150 mA even if the comparator is outputting 0 (voltage now in regulation), that's going to result in the output voltage overshooting the intended target?QuoteHmm. The Atmel SAM L10 and L21 chips seem to have incredibly good comparator specs, far better than any comparator IC or other MCU comparator I can find (including EFM32). Take a look at page 1029 (using the page numbers in the footer) of the L21 data sheet.
They're claiming 560 ns typical, 1.41 us max at 289 nA typical, 2.2 uA max; or 330 ns typical, 2.7 us max at 549 nA typical, 2.495 uA max. Those are all +/- 100 mV overdrive.
Dunno. 100mV is a lot of overdrive (you might use up all of that in a shunt resistor just on base level alone -- there are a lot of switching controllers out there that use a 50-200mV range current sense signal), but sub-1uA is awfully optimistic, even so.
100 mV is definitely a lot; I wish they provided numbers for 10 mV since that (I think) is more in line with the real use case here. Most MCU vendors don't seem to provide specs lower than 100 mV.QuoteAre these realistic or too good to be true? Heck, I'm pretty sure I've read a comment from you in some other thread saying Atmel's analog design process is poor, which just further makes me question how realistic their best-in-class numbers are.
Atmel is a big company, with a lot of products, designed by a lot of people, over a long time. That comment was about classic ATMEGA parts, which I heard from someone else (I haven't tested it myself, mind; other than the ADC and REF specs, which are right there in the datasheet). I haven't heard anything about the other families (XMEGAs, newer MEGAs, SAMs, etc.).
Fair enough!
I'm semi-curious about the SAM parts, but I'm not sure if my AD2 scope (which is pretty low-end; the AD2's value is in its portability, ease of use, and integration, not in raw specs of each feature) is enough to accurately measure that. Might be an excuse to get a proper scope though.QuoteHow big of an inductor are you talking? I noticed the LTC3388 requires 22 uH minimum and has recommendations up to 100 uH, which is on the bigger side of any regulator ICs I've looked at.
If you plugged in numbers like: 12V in, 5V 10mA out, 20kHz, into a calculator, you'd get something like 8mH for BCM. And proportionally more for proportionally lower currents, of course.
That's not so terrible (small, 10s mH inductors are certainly available), but inductances that large are I think hard to find with low losses and small sizes. Q is roughly proportional to sqrt(F), so the low frequency just keeps killing Q (and thus efficiency), and the small size doesn't help. The frequency of peak Q tracks with the linear size of the part, more or less, so a small part is extra disadvantaged at low frequencies.
Smaller inductances imply higher dI/dt, implying faster comparators to avoid fault conditions.
Classic engineering tradeoff, I guess -- higher inductance and lower switching speed/losses but increased inductor losses for the same physical size.
For now, I'm thinking the best thing to do is use a higher-power, faster comparator with a hysteretic control algorithm (which means the switching speed won't be limited to the available clock). I can probe it and optimize it later, testing changes like dropping the comparator speed (and power). Since standalone comparator ICs are specced for lower overdrives, I ordered an ST TS3021 which gets to about 50 ns typical at 20 mV. (TI has a similar part with similar specs, but it requires a higher input voltage. I could use it via the charge pump doubler, but why bother when the ST part is similar and supports 1.8V directly.)
note: The EFM32TG11 (and probably all the other EFM32s; I didn't look) require a higher (2.1V+) analog supply voltage for comparator settings faster than 3.7 us. It's doable, but for prototyping easier to just get another chip (plus it's specced for smaller overdrive).Can't you just use a standard CMOS logic level shifter circuit to drive the P-MOSFET?
MP1, MN2, MP2 and MN3 can be replaced with low voltage CMOS inverter gates, such as the 74LVC2G04. MN1 & MN4 can be the BS138 and MP3 & MP4, the BSS84.
Thanks! I'll simulate and probe that one to try to better understand it. -
That Zero999 circuit is actually quite neat
It seems quite power efficient, MN4 may also serve as a synchronous rectifier and you don't really need the low voltage part if you can devote two MCU pins to alternately turn on MN1 or MN4.
edit
There is actually some shoot-through during state transitions
I think two changes are in order:
1. Put 1k(?) series resistors right at the drains of MP3 and MP4. The connection to the output coil of course bypasses this resistor.
2. Really drive the circuit from two MCU pins, and ensure some short dead time when both MN1 and MN4 are off.
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So this, if I understand correctly, is about making sure the inductor isn't overcharged beyond its rated current limit (or it becomes a fire hazard).
Well, usually the transistor dies in 10-100us (probably longer at this small scale, or unlimited if you use a somewhat over- or under-sized part, as the case may be). Balls of wire and iron take seconds to ignite -- hence why dumb old fuses are adequate to protect wiring, transformers, etc. But yes, that would eventually be a problem as well.QuoteEven if the load current and inductor size were such that it was not operating in DCM, does hysteretic control not effectively take care of this? The comparator isn't going to trip until the output voltage drops below a certain point, which presumably means there's not some abundance of current stored in the inductor.
How can it? If the output stays low, the switch stays on, and on, and on...
A monostable timer, limiting maximum on-time, would be a nice addition. That way you can make the assumption that Vin < Vin(max) and L >= Lmin, and get a maximum dI = Vin(max) dt / Lmin that's within the transistor/inductor ratings.
You still don't know how long to turn off for; if the load is shorted, and the low side switch is synchronous, it could be very long indeed (a few time constants of the inductor's tau = DCR / L). If the low side switch is a diode, the diode drop is somewhat known (maybe 300-600mV for schottky), so you can expect the maximum off-time proportional to that and the supply voltage (using the equal-flux condition: the inductor spends as much time*voltage positive as negative).
Not that you'd likely use a synchronous switch here, but more for completeness.
We often diagram switching waveforms with certain ideals in mind, like assuming diode Vf = 0. But that doesn't happen to be a good assumption in a case like this. In this case (Vout ~ 0), Vf is significant, so we need to consider it. The case Vf --> 0 is still of practical use when we employ a synchronous switch, however; it's not just a fantasy.QuoteThis does make me question whether there's something basic in "buck converters 101" that I'm missing. The LTC3388 data sheet mentions ramping up the inductor current to 150 mA and then down to 0 mA, as if they're doing some kind of current monitoring similar to what you mention. (The LTC3388 uses hysteretic control.) The part I don't get is how they can do some kind of current control like this without affecting output voltage regulation. Surely if they keep the PMOS on until the inductor current reaches 150 mA even if the comparator is outputting 0 (voltage now in regulation), that's going to result in the output voltage overshooting the intended target?
They don't describe the "buck control" on the block diagram. It may be an ordinary peak-current-mode synchronous control, perhaps extra source terminals on the transistors (thus tapping off some load current, to a sense resistor, to sense amps/comparators), perhaps sensing drain voltage (which has a gross Rds(on) tempco (which can be corrected for), but is practical in terms of thermal performance).
Or maybe it's something dumber, like a constant-on-time control or something. Which is not uncommon among sync bucks: pulsing the inductor gives some dI, then you can watch just the low side switch's current to see 1. what peak current we got up to, and 2. where current crosses zero to turn off the sync diode.
Actual current consumption during operation might be much higher, but you don't notice it because inductor current dominates, of course; but then they disable everything inbetween, so the average consumption is almost nil.
You can't really do that with discretes, because few comparators/opamps are available with a bias control pin. And most that do, are higher voltage, low performance vintage designs, like the LM13700 -- which is quite useful in itself, but isn't going to be setting any speed records here. But in a monolithic design, it's a good plan, and probably what they're doing.QuoteFor now, I'm thinking the best thing to do is use a higher-power, faster comparator with a hysteretic control algorithm (which means the switching speed won't be limited to the available clock). I can probe it and optimize it later, testing changes like dropping the comparator speed (and power). Since standalone comparator ICs are specced for lower overdrives, I ordered an ST TS3021 which gets to about 50 ns typical at 20 mV. (TI has a similar part with similar specs, but it requires a higher input voltage. I could use it via the charge pump doubler, but why bother when the ST part is similar and supports 1.8V directly.)
Yeah, that'll do. Also MCP6561 family.
Here's an average current mode controller using discretes:
https://www.seventransistorlabs.com/Images/Flashlight2Sch.png
https://www.seventransistorlabs.com/Images/Flashlight2_Schematic.pngThat Zero999 circuit is actually quite neat
It seems quite power efficient, MN4 may also serve as a synchronous rectifier and you don't really need the low voltage part if you can devote two MCU pins to alternately turn on MN1 or MN4.
edit
There is actually some shoot-through during state transitions
I think two changes are in order:
1. Put 1k(?) series resistors right at the drains of MP3 and MP4. The connection to the output coil of course bypasses this resistor.
2. Really drive the circuit from two MCU pins, and ensure some short dead time when both MN1 and MN4 are off.
Yeah, doing it discrete, you want higher Rds(on), just overdriving a BSS84 directly will gulp 100s mA.
Note also that it's only latching while there's voltage available; in the discrete circuit, if both NMOS are off, the charge on either PMOS will eventually leak away.
The ring-of-two-inverters maintains state by itself, which may or may not be advantageous (if for some reason it's easier to generate brief pulses, that'll do; downside, it remembers what it was doing, which, if you didn't intend to say leave the switch in the 'on' position, well..). The main thing about inverters is, you can get much smaller transistors in logic gates than discrete, which is probably going to be the decisive factor. (If we could get 20V 20mA 50 ohm 4pF MOSFETs in singles, absolutely; if we're stuck between BSS84 and such, ehhh.)
Tim