Actually, my memory does still work properly. Zoom in a bit and watch for a while and the instability of the lock reveals itself.
280μs after.
-170μs before.
So in my case, I have a +280μs / -170μs variation around the locked point and it can swing from one extreme to the other and back again in just a few seconds. Maybe I'm expecting too much to think that it should be able to lock and hold the lock considering how small the variation is in mains frequency.
Obvious questions.
Have you checked the noise on power lines in that area?
Is there noise on the varicap control voltage?
Have you checked whether C101 C102 have dried out?
tggzzz C101 and C110 are a tants and C102 is an aluminum so all worth a check as this board runs like an oven!
Sitting right next to that bridge rectifier and the mains transformer, I can't exactly imagine it being particularly quiet either!
... So in my case, I have a +280μs / -170μs variation around the locked point ...
Grize, I'll do the same experiment tomorrow, but the quick check I did today seems to replicate what you are seeing almost exactly.
Sitting right next to that bridge rectifier and the mains transformer, I can't exactly imagine it being particularly quiet either!
Probably helps mode locking onto the ~50Hz
Actually, my memory does still work properly. Zoom in a bit and watch for a while and the instability of the lock reveals itself.
280μs after.
-170μs before.
So in my case, I have a +280μs / -170μs variation around the locked point and it can swing from one extreme to the other and back again in just a few seconds. Maybe I'm expecting too much to think that it should be able to lock and hold the lock considering how small the variation is in mains frequency.
I don't think the filter caps in the loop filter should be so critical. Tantalum caps usually fail short, but not with slowly rising ESR. LOW ESR is likely also not really needed. It would be more the capacitor at the supply that could be a problem.
Could be due to not having the clock set close nominal free running frequency and the PLL having to work hard resulting in the Glug Death until it locks? Glug death only flashes up for about 4 secs and previous test the glug death signal is only high for about 0.8 secs on start up anyway, so not sure if this is related.
The placement of the 4046 for the PLL is really odd. With resistors in the 100 K range I would consider the VCO control signal sensitive, even if there is a 1 µF capacitor. I think this deserves a .
The ceramic vs. plastic case for the VCO chip should not make much difference - this part is not about precision or lang time stability.
If your oscillator board is way off frequency, it might explain the much larger variation that you have once the PLL actually locks and possibly explain the slightly longer time to lock from power on. I doubt it has anything to do with your glug death though as all the glug timing is derived from the main clock. Logically, if it's a bit fast or slow when it starts, the rest of the timing will also be affected the same way and it shouldn't make any difference.
I'm thinking that your glug death problem lies somewhere with IC313. I notice it has two split pads on the outputs - SP303 and SP302. On my machine, both are soldered. The -CLR signal which is supposed to reset the watchdog so that it doesn't assert GLUGDEAD comes from IC313 via IC314 and has a test point at TP304. IC424 plays a key role in switching the glug timing between the full speed forcing wave frequency of 24KHz for 4 digit measurements or the much slower 1.5KHz speed used for more digits. If there's anything that's not 100% with IC424, it could mess up all the timing as the whole circuit starts up.
I'm grasping at straws here as the whole timing circuit is very complicated, but there does seem to be some condition which isn't established properly as your meter starts up, so these areas would be good places to look at.
Just saw your new post as I went to post this. That ripple really doesn't sound nice, nor does the jitter. I'd certainly be having a look at the smoothing capacitor for that 5V rail. You do have a nice ceramic package there for your VCO chip, while mine is the humble plastic package. If you have a signal generator that you can generate a 49.152MHz sine wave with, it would be an interesting test to pull the clock board out and inject 49.152MHz from the signal generator at the clock board's output pin and see if it makes the glug death problem go away. It would, at least, determine if the clock board is the problem or not.
Here is pin 2 (ch1) and pin 11 (ch2) of IC301, from power up:
and zoomed in to the trace once both signals are running:
Sorry for the photos, but for some bizarre reason, the utility I have always used to grab screen shots from the Rigol suddenly bombs out trying to connect to the scope. The noise and over/undershoot on the traces is purely from my crap, but safe, probing setup.
It is well possible that during start up the 4 nines modes is used for a quick self test.
The scope trace from the start-up looks a little like there is something on that kind going on un the center of the screen.
A brocken IC310 is a possible explanation. Maybe also check to solder joints, not just QC,QD, but also the C and D inputs.