-
AD9361 based SDR - 70MHz-6GHz Tx and Rx with FPGA and USB 3
Posted by daveshah on 20 Dec, 2016 18:48 -
I've been wanting a bit of a PCB design challenge for a while, so I've decided to build a SDR using the AD9361 integrated transceiver chip (70MHz-6GHz, dual channel Tx and Rx) with an Artix 7 FPGA and FTDI USB 3 interface. I've finally received the boards and run some simple tests which seem to be working - after a couple of small bodges to the PCB (adding a missing Schottky to a buck converter and cutting the JTAG connector shroud so the IDC connector on the ribbon could fit).
The Github URL for the project is https://github.com/daveshah1/RFToolSDR. At the moment the repo only has the hardware designs; I'll release the FPGA VHDL and Linux software in the next couple of weeks as I finish them and fix the bugs. I'm also looking into adding GNU Radio support.
I got the PCB fabrication and assembly done by ALLPCB who seem to have done a very good job - I didn't fancy doing the tiny pitch BGAs at home. Their part sourcing got quite a good deal on some parts (which I'm hoping are legit, they seem to work at least) so there wasn't actually that much cost difference compared to building a few boards myself.
-
Very nice work 👍🙂
Are you considering selling some of these. I might well be interested for the up to 6GHz coverage it provides.
Best Wishes
Fraser -
Very nice work 👍🙂
Are you considering selling some of these. I might well be interested for the up to 6GHz coverage it provides.
Best Wishes
Fraser
I have thought about selling a few. I'm not sure what the regulatory situation for a product like this is, particularly given it can transmit at >20dBm over a wide frequency range. I'd also have to price it at around ~£500-600, although now the single channel AD9364 is available I could possibly make a single channel version a bit cheaper. -
I noticed that you are biasing all of the amplifiers with a single inductor, is that providing good enough isolation over the required BW? Do you have any simulation results?
BR -
I noticed that you are biasing all of the amplifiers with a single inductor, is that providing good enough isolation over the required BW? Do you have any simulation results?
BR
I've done some simulation in QUCS but mostly for the Rx path, and Tx power amplifiers. Wideband performance at least for Rx isn't going to be great as the impedance of the AD9361 is all over the place and hard to match - but in the 500MHz to 3GHz bands using the LNA inputs it should be pretty good.
Likewise the band limited 500MHz-3GHz PA outputs should be OK, in retrospect the single inductor feeding the AD9361's internal PA for the full range output was probably a bad idea. It is however how AD do it in their reference design.
Once I've fixed some software and FPGA issues I'll try and do some basic tests and report back. Hopefully in the new year I'll be able to use a SA and RF signal gen at uni to do some more serious testing. -
If there's one thing I've learnt as I continue to test things; it's read the datasheet carefully!
As well as the aforementioned missing Schottky; I also failed to see that the LNA I used had an active low enable (to be fair there was no bar or other indication in the pin diagram). This was easily fixed by bodging the PCB, unlike another major issue preventing dual channel receive. It turns out the AD9361 requires corresponding inputs to be used on both channels, so you can use RX1B and RX2B but not RX1B and RX2C for example. This is problematic, unless currently undocumented registers appear to fix this which I find unlikely, as I only connect to RX1A, RX1B and RX2C.
Anyway I've attached a screenshot of the simple software I'm working on, showing 5GHz WiFi. After Christmas I'll try to do some wideband sweeps and test the transmit path.
-
Do you mind saying how much it was to get the board assembled?
-
I've been wanting a bit of a PCB design challenge for a while, so I've decided to build a SDR using the AD9361 integrated transceiver chip (70MHz-6GHz, dual channel Tx and Rx) with an Artix 7 FPGA and FTDI USB 3 interface. I've finally received the boards and run some simple tests which seem to be working - after a couple of small bodges to the PCB (adding a missing Schottky to a buck converter and cutting the JTAG connector shroud so the IDC connector on the ribbon could fit).
so this is pretty similar to the USRPB100B200 which is based on AD9364?
Would you expect anything significantly different in terms of Rx noise floor, dynamic range, or other performance figures?
Is it feasible to assemble the boards by hand?
thanks! -
Do you mind saying how much it was to get the board assembled?
About £1500 for 3; fortunately I have a few friends interested in using the hardware so not too expensive per unit. -
so this is pretty similar to the USRP B100 which is based on AD9364?
Would you expect anything significantly different in terms of Rx noise floor, dynamic range, or other performance figures?
Is it feasible to assemble the boards by hand?
thanks!
I think it's the B200 series that use this chipset. I haven't looked in detail but I think at least compared to the cheaper one (B200mini) my device has lower NF on the LNA inputs; higher max Tx power on the PA outputs; better Rx input protection and more FPGA horsepower.
Hand assembly isn't possible but assembly at home with a stencil and reflow oven should be if you have enough experience. -
Looks pretty good. I was planning on trying this project myself eventually, although probably with LMS6002D or AD9363. I heard lime is also coming out with a 12ghz sdr chip, which would be pretty interesting, but their company is kinda washy it seems, so we'll see if they end up taking it to market.
-
Looks pretty good. I was planning on trying this project myself eventually, although probably with LMS6002D or AD9363. I heard lime is also coming out with a 12ghz sdr chip, which would be pretty interesting, but their company is kinda washy it seems, so we'll see if they end up taking it to market.
I looked into it and reckon a design with off-the-shelf parts - not a single SDR chip but mixers, VCOs, frequency doublers for the VCO etc - up to 30GHz would be quite doable if you had the time and money. It might even be my next project once I've worked more on the software for this one. -
27dBm max input power is very high. Do you anticipate a use for being able to input half a watt? Or is it just to make it more robust?
-
27dBm max input power is very high. Do you anticipate a use for being able to input half a watt? Or is it just to make it more robust?
Just for robustness as I'm quite a careless person
. Decent protection was needed anyway as the PA outputs are capable of 20dBm+ and I didn't want the board to be able to be destroyed with itself.
-
Well, I am using a USRP B200 at the moment, but once you get it working with GNU radio I would consider buying one.
-
Excuse my ignorance of this RF voodoo but just wondering how good a spectrum analyser you could implement with this?
-
Excuse my ignorance of this RF voodoo but just wondering how good a spectrum analyser you could implement with this?
In theory a basic spectrum analyser could be implemented but it's not the ideal platform.
If you want to look at less than 56MHz of bandwidth at a time though, it's pretty good. Above that you have to sweep the centre frequency which is relatively slow at the moment; although this could be improved a lot (I believe lock times down to 50us or so are possible) by moving the AD9361 interface code from the PC (with a relatively high latency USB interface) to a softcore on the FPGA with direct SPI access.
Another problem is the LO architecture used will result in fairly significant spurious responses as it is generated from a divider with fairly high harmonic content. For example 800MHz LTE signals can be observed to a degree at 267MHz as the LO has a third harmonic spur at 800MHz. -
Yep, slow sweep and bad spurs are the biggest issues. Phase noise might be another. It's the sheer variety of spurs that adds excitement, coupled with the fact that spurs in your SDR/SA would sometimes be difficult or impractical to tell from spurs in your DUT (especially if the SA spur drowns out the DUT spur).
How severe these limitations are depends on the application, of course. For standards, emissions, or performance testing, not knowing equipment spurs from DUT spurs is a showstopper. In other applications, the shortcomings of SDR can even turn into strengths! At work I deal with devices that have uplink and downlink frequencies separated by up to 50MHz, but I can use a $20 1MHz SDR to get presence+timing information out of both directions of traffic by putting the antenna somewhat near the device. The un-tuned signal (~12kHz wide) overloads the receiver and leaks all the way across the 50MHz into the 1MHz capture bandwidth, interleaving with the in-band signal but showing convenient contrast in amplitude. The SDR dongles are cheap and light enough to hand out and they make it easier for the SW guys to figure out "is this thing on?" type problems all on their own
Anyway, here's an example of possibly non-obvious trouble that spurs can cause.
Red, White, and Blue: the SA44B economy spectrum analyzer looking at a BG7TBL broadband noise source with 0dB, 20dB, and 40dB attenuation. It has two LO frequencies. Different LO = different spurs, so it can reject spurs that it sees in one and not the other. A step up from SDR, but a step down from a proper SA.
Black & Amber: a fixer-upper SA with proper mechanical attenuation relays, YIG preselector, and YIG LO looking at the same BG7TBL. The calibration is about 10dB off, but the point is the overall shape of the noise and how different it is from what the SA44B shows.
One of them lies, despite the attention its designers paid to its shortcomings, and one of them tells the truth. Don't get me wrong, it's not a dig at SignalHound -- their BB60C would have had no problems with this signal, and they call out the broadband measurement problem specifically in the SA44B datasheet -- but it *is* a limitation of the architecture that SDRs would share (except worse).
That said, I'd love to see some good SA/VNA software for SDRs. A SA/VNA that you can afford has infinitely better performance than one you can't.
-
There might be a few tricks to reduce the spurs - at least the LO harmonic related ones - that I'll hopefully play about with at some point (too many ideas, not enough time...).
If all the signals of interest are known to be continuous then software correction seems possible - e.g. shift the LO by 1MHz and any signal not shifted by 1MHz is spurious.
The next options would involve extra hardware. In theory building an up converter that converts a smaller range - say 0-3GHz - to a fixed 6GHz shouldn't be too difficult to build and would probably reduce many of the spurs. Depending on the VCO/PLL used for the converter it might also improve sweep speed.
-
Software spur removal would would still have issues with any signals wider than the difference in LO frequency (see: the SA44B above) or non-LO spurs (as you mention) and it would come at the cost of halving the already slow sweep speed. Sure, you could design a sweeping VCO and selectivity filter, but that would already be 3/4 of the way to a traditional SHSA design. Might as well go the extra 1/4 to get the extra performance and lower cost.
Why not focus on the SDR's strengths and use your programming hours to focus on signal capture and analysis instead? AFAIK you still have to cobble together a half-dozen flaky and under-UI'd tools to approximate SignalVu-like analysis for unbranded SDRs, which is sad. Seems like there's still plenty of room for someone to integrate the tasks, even if it's really just GNU radio inside
-
Pretty impressive
. How did you supply enough current from the USB connector to power the FPGA/PA/LNA etc...?
Why did you need an onboard ram?
