Which address decoding is better for memory interfacing. I think we can do any of them. But I am confused which is more beneficial for memory interfacing. My inituition tells full decoding but why I don't know.
Partial decoding is only for super-compact, super-cheap applications that have no expansion possibilities planned.
Otherwise it's a thing of the past. Modern CPU systems use full decoding, with a CPLD it's easy and cost effective.
Interfacing from what? What non-vintage processor still has a generic external parallel IO bus where this would even be relevant?
Also what Benta said: there is little reason to do partial decoding. If it comes to it, a single cheap CPLD can do address decoding to drive a huge number of chip select lines.
Both work. It all depends on what you are trying to do and what resources you have. If you building your own system for learning, you won't be expanding the system, and you only have standard decoders, it's fine to partially decode. It's not as if the memory will suffer if you don't fully decode. But some address ranges will be aliases of others.
Partial decoding consumes more of the usable address space because the same memory appears at multiple address locations. If you do not need the wasted address space for anything else then it makes no difference at all. There is typically little reason to bother with partial decoding anymore though, a small CPLD can easily fully decode an entire 16 bit address space.