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I have been poking at trying to build a custom, adjustable, fairly wide frequency divider. My original purpose is to get a seconds pulse (with a flexible second definition). More specifically I would like to get a 4096/3600 Hz signal, and the possibility of fine tuning. So far I have come up with this chain of 74LV163-counters. I believe it should be workable for an input of below 20MHz.
To get my 4096/3600Hz from a 32768Hz crystal I would need to divide by 28800 which my divider is totally overkill for. However, I thought it would be sweet if I could use a 10MHz input, since 10MHz oscillators come in more interesting varieties. That would require a 8789062.5 division factor, and fractions is not something my divider knows..
So I have thought of two different solutions to that. Either a combination of a pre-scaler and a PLL to divide out a factor and multiply in some factors of two, before feeding that into the divider. Or to double up the output from the divider by some multivibrators. I'm trying to think of pros and cons with the two set-ups. Perhaps I should just try to implement both, and either both, one or none could be used or by-passed, to have access to the best of both worlds.
Pre-scaler/PLL- Pros
- Easy set-up
- No jitter
- Allows d-latch divide-by 2 on output for (true) 50% duty cycle
- Buffers the oscillator output
- Cons
- PLLs seem to be mostly 3.3V
- Expensive
- Needs a minimum input frequency
- It just feels a bit like cheating...
Multivibrator- Pros
- More flexible input voltage
- Adjustable output duty cycle, without any further division
- Simple wall clock movements require complementary alternating pulses every two seconds
- Cons
- Fiddlier
- Jitter, needs oscilloscope to be set-up properly (quite a bit of jitter would be tolerable for a clock)
- Still needs a buffer for the oscillator(? A simple logic buffer should suffice(?))
Any thoughts, ideas or suggestions? Am I re-inventing the wheel in square form? This is in ways intended to be part of a "basic" build-a-clock-to-prove-worthy project. Meaning I want to stick to fairly simple logic building blocks, and certainly not use micro-controllers or other magic black-boxes... In addition I'm planning for my clock to have separate counter and display stages, but those will be for future topics
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The usual 10 MHz (and 32 kHz) oscillators are not that stable that is would make a difference not having finer than integer division. If finer adjustment is needed I would fine tune the crystal.
A multivibrator as a clock doubler a the output causes quite some jitter, and may need extra adjustment. -
Kleinstein's point about oscillator stability was on point. Note that you're talking about a division factor of
about 9*10^6. Any reasonably priced crystal oscillator (a TCXO) is going to get you to a few parts
per million in frequency accuracy, even without aging. By the time you get to ovenized oscillators, you're
talking either real money, or a surplus unit.
So, what would it mean to be off by 1 PPM in a clock? You'll gain about one second every twelve days.
As for PLLs, building a discrete PLL is an adventure. It doesn't always end well, but the learning along
the way is hard to match.
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10MHz input -> Xor gate with a small RC network between the 10MHz input and the other input of the gate to produce ~25ns of phase lag = 20MHz output (You could even use the propagation delays thru the other gates in the xor package to get you the delay you need)....
No need for a PLL if all you want is to double a known clock frequency, if the clock was a sine wave you could even just use a diode ring mixer.
But yea, there is good learning in a discrete PLL.
regards, Dan. -
I know it would require a decent oscillator to fully appreciate the exact division. About 100ppb accuracy to be comparable to a change of 1 to the divider, right? There seem to be a few 100ppb oscillators that aren't prohibitively expensive. And there is the odd possibility I pick something used but interesting off from ebay... Also aging is a (progressive) absolute offset? So the ability to make small adjustments to the division factor would come handy to offset that. Anyway 10MHz sources do come in more interesting varieties.
My custom clock idea is to have 64 "seconds" to a "minute", 64 "minutes" to an hour (regular), 24 hours a day. or in octal that is 100 "seconds" to a "minute", 100 "minutes" to an hour, 30 hours a day, or simply put 300000 "seconds" a day. I call it my octoclock,and I think it makes great sense
It's also fairly intuitive to translate to into the regular base 60 clock.
But I also want it to be general enough to play around with other clock divisions schemes. The lacking factor 2 in my particular case is what has been bugging me the most.
I think I wouldn't want to muck around with building my own PLL at this stage.. I got myself a couple of CDCVF25084 to play with. They are a bit pricey, and they don't want a too low input frequency. I'll put those in the list.
I think the kind of jitter with my vibrator-multiplier rises wouldn't be really bad since it's only every other pulse that is a wee bit off. Adjustment would be needed, probably using an oscilloscope. I think that is something acceptable in a device obviously aimed at enthusiasts
10MHz input -> Xor gate with a small RC network between the 10MHz input and the other input of the gate to produce ~25ns of phase lag = 20MHz output (You could even use the propagation delays thru the other gates in the xor package to get you the delay you need)....
This sounds really interesting. I need to experiment a bit with that. Just the kind of idea I was hoping for, something I would never have thought of myself
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I actually had a third idea. Letting a 163 counter start at 1 the following sequence is givenCode: [Select]
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Looking at Q2 output it does 4 low-high transitions during 15 clock cycles. That is the input divided by 15/4 with some jitter. Chaining two of them make a divide by (15/4)^2.
Dividing my earlier modulus 8789062.5 by (15/4)^2 gives 625000 which happens to be a 20-bit number. I must have done something different, I can't seem to remember it lined up so well with 4-bit counters... That would be a fairly specific solution to my particular division though. And the adjustment increment is on the same scale as seconds in a week, which is fairly ok.. The jitter should virtually go away after dividing by another 625000.
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Just lucky to spot it before someone else point it out.. My vibrator frequency doubler would be of little help to me. To get the signal I need to double I would need to divide by 17578125 which my 24-bit divider doesn't do anyway
[Programmable logic stuff]
That's actually really interesting as well. I was randomly in on the Mojo FPGA Kickstarter. I had the idea it would be fun to learn some programmable logic stuff. Never had the time, and most of all not the motivation to get started. Working on implementing the counter I desire could be just what I need to get into it. Thanks for reminding me
I'm not at all familiar with how competent the different size programmable logic families are. A counter could perhaps be done in something simpler than a full-blown FPGA.
Counting fast enough, at the correct modulus, setting off pulses at certain pre-determined and just almost equally spaced intervals would be a pretty decent factional divider as well.
I'm still implementing this with counters and stuff. I already have most of the parts, and I think it will be a nifty little device just for fun
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So, moving forward with this, I have a few further questions.
- I'm planning to use a BQ24232 battery management chip, feed it from USB, and have a single 18650 cell for backup. The BQ-chip is enough in terms of battery protection, right?
- The circuit will be running on 3.3V from a TPS63030 (or 63031 rather for 3.3V). I'm going to use these displays I built. If the board loose power I want the displays to power down. I would also like to be able to run the displays on a different voltage. So I thought I would add a second TSP63030 with a trimmer to allow for voltage adjustment. Then use the power good pin on the BQ24232 to disable the TSP when power is lost. This should work, right? What happens to the TSP output, does it float or end up at GND or the input voltage, or what? Should I use a transistor to cut the power off instead?
- When the TSP63030 is disabled, I don't want to feed power into the inputs of the displays (they are ATtiny IO-pins), since the displays are no longer powered, and I shouldn't exceed VCC on them. I was looking at 74LVC245 transceivers which I could tri-state on the same power good from the BQ24232, and I should be safe, right?
- However, if I run the displays on a different voltage I'm likely to cook one thing or the other (depending on which voltage is higher). How do I solve this? Is there a buffer/transceiver/driver thing with open drain that I could use. The ATtiny has built in pull-ups, so that would work, no? Or use current limiting resistors and exploit the input protection diodes of the ATtiny. Is there a better way?
- The displays have separate pins for the LED supply. So I could instead use the second TSP to power only those. But in that case I would need to make sure the LED supply does not exceed the supply of the ATtinys, their IO-pins do not handle that. (Well I suppose the voltage drop across the LEDs give some headroom). In this case all the ATtinys will still be powered, but the LEDs should be the main power consumers.
Edit: The 3D-view may look funny. I just used components I found with roughly the same physical properties of the real ones.. Those power LEDs should be hex rotary selection switches.