Every time I have to laugh a lot about the standard errors that are made at Linear power supply circuits here on the forum...
Why let's take the last schemes, C8 100uF, and R13 100 Ohm, you must be jokink...
If you ignore this, you will always start crying.
Kind regards,
Blackdog
If you are aware of my technical remarks and you know that they are correct, why didn't you help the people in this topic?
You have done a nice LTSpice simulation above - you may try with say 15V output, switching from 10mA -> 5A -> 10mA output current (with, say, 200ms period and 10us edges) and adjust the loop when required..
The fact is when the control loop is "slow" an abrupt load change at the output will propagate "slowish". Thus it will not track properly.
If the user not1xor1 made the LTSpice source public, we could have played with it and finalize the efforts of the contributors..
Hi,
Imo, try this if you want to test.
Remove Q3, R5, C1 and R7.
Use a diode between R1 (make him 100 Ohm) and the anode of the diode on the base of the BD243.
Place a 4K7 resistor between the base and the emittor of the BD243.
Make the currend source I1 10mA.
Make C2 220pF (play with it for good stability)
Make V3 30V
Connect V2 opamp power supply to V3, so remove V2.
Watch your opamp inputs, are they still connected the wright way in this test setup?
The problem with the schematic and many schematic of power supplys.
The average opamp has between 55 and 65 degrees phase margin.
And for a good stable linear power supply, you need at least 45 degrees phase margin, 60 is better.
If one or more transistors are behind the opamp, these transitors slow down the loop in which the opamp in the transistors is placed.
These transistors all eat a bit of the phase margin.
Below the 30 degree phase margin you come into the danger zone.
Please , please, please, do not disregard this information, because it always goes wrong if you do this.
It doesn't matter if you are developing a linear or a switching power supply or an electronic dummy load, this is always the case!
See my previous post with links to info on this topic from the TI website, first class info from TI!
Kind regards,
Blackdog
But I get the impression that people are getting more and more lazy while the info with a little search is easy to find.
That's why I have to laugh and sometimes maybe cry a bit...
You will have, no doubt read the posts about the compensation being too heavy. Don't worry about this, it is intentional, as I have previously stated. There is little point in fine tuning the compensation until the PSU has been prototyped and tested. Once that is done we can optimize the stabilization, if necessary, by a few simple modifications, mainly capacitor changes.
In common with many PSU designs, the approach is that the opamp voltage servo loop defines the absolute DC output voltage and also provides the very low frequency currents, the big electrolytic capacitor provides the medium frequency currents, and the solid capacitor (ceramic) provides the high frequency components. You can get a more in depth coverage of this area from the manufacturers application notes and from individual component data sheets.
[...]I'll see if I can simulate it.Be great if you did do a bode plot of the circuit.
I simulated just AC. The bodeplot doesn't look so good. It needs some more work on compensation.
not1xor1
I had missed this simulation that you did for the pre reply #89 circuit. Thanks a lot- very interesting.
But you have omitted one fundamentally important component: R19 (10K)
What is the battery on the non inverting input of the opamp doing there (the reference voltage is the variable).
Also in #89 revised schematic:
R13, R20, and R21 are 56R.
All small signal transistors are BC337/327
D1 (D5) has been removed and replaced by a trace
R4 has changed from 1k to 56R
not1xor1
I had missed this simulation that you did for the pre reply #89 circuit. Thanks a lot- very interesting.
But you have omitted one fundamentally important component: R19 (10K)
What is the battery on the non inverting input of the opamp doing there (the reference voltage is the variable).
Also in #89 revised schematic:
R13, R20, and R21 are 56R.
All small signal transistors are BC337/327
D1 (D5) has been removed and replaced by a trace
R4 has changed from 1k to 56R
You're right. I had overlooked the fact that the reference voltage was on the inverting input. Of course the local feedback is affected by the resistor in series with that input, but there is little difference between 10k and 11k (i.e. the pot at its minimum) of source resistance.
I also changed the transistors and the resistors, anyway the bodeplot is still ugly .
I tried to compensate the circuit in a different way and it improved a little (phase margin in the 50-70° range according to the load). But I've no idea if that might work in the real world. Later I'll run a transient load simulation.
Hi Spec,
Thank you for the insight of my psyche, I didn't know that yet, keep up the good work!
not1xor1
I had missed this simulation that you did for the pre reply #89 circuit. Thanks a lot- very interesting.
But you have omitted one fundamentally important component: R19 (10K)
What is the battery on the non inverting input of the opamp doing there (the reference voltage is the variable).
Also in #89 revised schematic:
R13, R20, and R21 are 56R.
All small signal transistors are BC337/327
D1 (D5) has been removed and replaced by a trace
R4 has changed from 1k to 56R
You're right. I had overlooked the fact that the reference voltage was on the inverting input. Of course the local feedback is affected by the resistor in series with that input, but there is little difference between 10k and 11k (i.e. the pot at its minimum) of source resistance.
I also changed the transistors and the resistors, anyway the bode plot is still ugly .
I tried to compensate the circuit in a different way and it improved a little (phase margin in the 50-70° range according to the load). But I've no idea if that might work in the real world. Later I'll run a transient load simulation.