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Without connecting lines, how do I know I've spotted everything connected to IC3 pin 6? Arguably it is possible on this small diagram, but it becomes impossible on larger diagrams.
I don't make schematics that take more than a few pages, but for work I have to read schematics that are 20+ pages from time to time. And most of them drawn in that "disconnected" style. And I personally prefer it.
And they all come from different authors, so there is some sort of agreement there.
With search you can find all the places signal is mentioned, if you need to know this information. But in many cases you don't really. Especially for things like 144-pin FPGAs, or 100-pin MCUs.
And doing point-to-point lines for MCU + SDRAM is virtually impossible.
Some schematic capture software can actually put page numbers where this signal is used in parenthesis after the signal name. This helps as well. -
Without connecting lines, how do I know I've spotted everything connected to IC3 pin 6? Arguably it is possible on this small diagram, but it becomes impossible on larger diagrams.
With search you can find all the places signal is mentioned, if you need to know this information. But in many cases you don't really. Especially for things like 144-pin FPGAs, or 100-pin MCUs.
You make presumptions that are often not valid - particularly for large designs, designs that are important for more than a short time, or for designs produced by a different company.
How do you search a jpg?
How do you search a paper document?
How do you search an Altium (etc) schematic where you don't possess Altium?QuoteAnd doing point-to-point lines for MCU + SDRAM is virtually impossible.
No, it is entirely possible and easy - as has been demonstrated in professional designs since the 1970s (and earlier)!
What you do is have each address line (data/control) coming from a pin and entering an address bus (data/control). You then route the bus around the diagram. Typically the bus is shown as a wider line.
The first example that comes to hand is shown below: a small snippet of one diagram for a Tek 2445 scope.QuoteSome schematic capture software can actually put page numbers where this signal is used in parenthesis after the signal name. This helps as well.
That can help a bit, but isn't sufficient.
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Your schematic is actually very decent.
I don't do this. Instead I'll group D1 through D8 do that they're all bunched up together with obvious gaps to the nearest components. The Ref Des is left by each component, but the value fields (all 1N4007) are stacked on top of each other, with every one visible.
Other posters have already made their (good) comments, I won't repeat them.
Thus I'll only add that some times in very tightly drawn schematics, when one has several identical devices clustered together, it helps to do a global description like:
"D1 thru D8: 1N4007"
instead of listing each device:
"D1 1N4007"
"D2 1N4007"
"D3 1N4007"
and so on............
It may not matter on a short name like 1N4007, but nowadays some components have humongous part numbers, and it adds to visual clutter quickly.
This way, if one of the values is wrong, you can still see it. Only if they're all the same can you read the value.
Other rules of mine:
Pull up/down comps are always vertical.
Use the same spacing across the entire schematic. If your symbol pins are on a 0.1" pitch, your entire grid should be on that pitch. Associated wires (eg all wires on a peripheral bus, data, r/w, cs) should be spaced 0.1" apart. Use a gap of at least 0.2" for unassociated wires.
Never change net names as your signals traverse a Hierarchy, unless it can not be avoided (multiple reuse of H-Blocks). In this case if the signal name outside of the H-Block is FRED and the H-block name is BLOCK, then the signal name inside the H-block is BLOCK_n_FRED. This will be controversial as it will slow your schematic capture, but it will pay you back ten fold when you try to debug.
Never forget that schematics are the EE's art. They should be beautiful. You should look at a sheet and instantly know what is going on. Not with every component, but you should see purpose and dataflow at a glance.
Never be scared to create a new schematic body and move the pins around to achieve simplicity.
On really big schematics, come up with a net naming convention before you start.
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Dont break schematic into very small sections, like second example. Dont leave it as very big sections, like first example. Also current goes mostly from top to bottom, and from left to right. Except feedback.
And change to IEC symbols for passive, keep using ANSI for active. Trust me, schematics look 100 better that way. -
Never forget that schematics are the EE's art. They should be beautiful. You should look at a sheet and instantly know what is going on. Not with every component, but you should see purpose and dataflow at a glance.
Very true; my emphasis added.
Anything that impedes seeing those thing is unwelcome. -
Oh no. Oversized PNGs! another one of my pet peeves. It wastes Dave's bandwidth.
The file sizes of the images posted in this thread are much too large!
dsharp02, tggzzz,
How did you make those files so big?
I've converted the colour one to 8-bit indexed and the monochrome one to 4-bit with no transparency. Now look at how much smaller they are! There's no need for low compression ratio 32-bit colour images for schematics.
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Never forget that schematics are the EE's art. They should be beautiful. You should look at a sheet and instantly know what is going on. Not with every component, but you should see purpose and dataflow at a glance.
Very true; my emphasis added.
I always say that a schematic is an electrical roadmap -
Whats the point of a Schematic.. Its to convey information to the people that need to read it.
If the schematic is just a sketch on my notebook, for me to remember to do something, then if its a bit rough, its not important..
If the schematic is somethign that i'm going to use by myself, then there are a lot of assumptions that i can make and i can be a bit less careful with it.
When i have to share it with others, then i really have to be careful.
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Your 2nd revision is definitely an improvement from the 1rst (although, the 1rst wasn't so terrible in my opinion). In the 2nd version, you might have gone a bit overboard with the segmentation blocks. In general, I try to keep my analog circuits more continuous, so I can see at a glance the purpose of the circuit and, usually, the topology of the implementation. But for digital circuits (i.e. IC-to-IC serial connections) I almost exclusively use net labels. Attached are some examples. Everyone does have style differences, so it's difficult to quantitatively say one style is superior. Of course there are general rules of thumb and conventions (as others have already explained). Following an employer's conventions could be one of the most important considerations.
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Yes, this is a much better example of what I was trying to covey with words. Digital -> net labels, analog or standard circuits -> connected.
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I was about to say, "your schematic is already better than many others I've seen; for a start, it actually connects the parts together"... and then I saw the second "improved" version.
A schematic is not a bunch of parts with netlist labels. Count me as one of those who liked your first version more. I've read a lot of laptop schematics and they're all scattered, barely-connected blocks, not because it's better, but because it's easier and lazy. In fact I believe those are automatically generated "schematics" from the netlist. IMHO if you need to use Ctrl+F (which does NOT work on an image) to see where some signal goes, you've failed. -
I don't see how buses help you find all the places signal is used. Buses are basically the same as net labels, except you don't need to run additional thick lines everywhere.
It is not lazy, it is practical for large digital circuits. I don't remember when was the last time I actually had to look at a printout of a schematic for normal work.
I do printouts for reviews, but there I typically want to put marks next to things I've checked, so PDFs are not very practical for that. -
There are times when the schematic symbol of an IC just won't allow for neatness and sometimes it's good to create your own, power pins top and bottom and I/O's left and right. Some EDA package have a # of symbols for each IC but when they don't and you still wish to show connectivity and signal path flow the solution is to build your own.
It's good to see a well laid out schematic, it serves as a record of the various calcs made in determining the values used of individual components. Sure scribble down a concept but take the time to draw a decent schematic too.
The more you do, the faster and more polished you become. -
Oh no. Oversized PNGs! another one of my pet peeves.
How did you make those files so big?
I just did a screen cap and cropped it to size. My apologies for not taking the time to shrink them down a bit, I'm on a fast connection and didn't think about the impact to bandwidth. In the future I'll try to be more careful with my attachments.
Dave -
I don't see how buses help you find all the places signal is used. Buses are basically the same as net labels, except you don't need to run additional thick lines everywhere.
It is not lazy, it is practical for large digital circuits. I don't remember when was the last time I actually had to look at a printout of a schematic for normal work.
I do printouts for reviews, but there I typically want to put marks next to things I've checked, so PDFs are not very practical for that.
I'm sorry, I could not disagree more. A schematic has two functions:
1/ Graphical generation of the netlist.
2/ To convey information.
You've met the criteria of 1/, but this type of schematic utterly fails to convey information. Someone not familiar with the design will struggle.
It is poor practice to force engineers to use CTRL F to hunt down each and every connection, then hold that connectivity in their heads whilst they track down the next net.
Using net names to link blocks everywhere IS just laziness. I don't agree it's about being practical, both methods can be done, so both methods are practical. Sure your method is faster to draw and sure, you will be able to follow it, so why bother putting the extra effort in?
Drawing the connectivity not only makes debug easier, it makes review easier too. I believe it makes design more rigorous too, working graphically gives you a perspective you don't get otherwise. So whilst it may take longer to draw connectivity, you will have a better schematic and that will save time in the years that follow capture. Surely that is more practical than banging out any old rubbish as fast a possible?
Don't get me wrong, I have tried it your way. My old employer wasn't very pleased when I had to tell him that he had to spin a 2000+ component, 16 layer, multi $1000 PCB because someone
had made a typo on a net name. The blind and buried net on the otherwise perfect board couldn't be reworked.
Cadence released a tool some years ago that allowed you to generate netlists from spreadsheets. Component,Pin, Netname. I don't think it's very popular for exactly the reasons I've given.
I think we may have to agree to differ. -
It is poor practice to force engineers to use CTRL F to hunt down each and every connection
But I never need to hunt down all connections. I just don't see how this is a use case for anyone. I'm typically interested in a few pins related to a part I'm working on at the moment.Drawing the connectivity not only makes debug easier, it makes review easier too.
I guess it is a matter of taste then. Because that statement is false for me.
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It is poor practice to force engineers to use CTRL F to hunt down each and every connection
But I never need to hunt down all connections. I just don't see how this is a use case for anyone. I'm typically interested in a few pins related to a part I'm working on at the moment.
Of course you don't. It's your design, you know what's going on. Try working with a team of schematic engineers spread across the globe. Or try handing over your design to a team who don't understand it. The easier the schem is to read, the less they bother you...
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It's your design, you know what's going on.
As I said already, I don't design anything even remotely complicated. But I do have to work with schematics supplied by other people/companies. Some are very big. And most are designed in a way described by Eric_the_EE. I have no problems whatsoever getting information that I need from them.The easier the schem is to read, the less they bother you...
The problem is in what you consider "easier". To me it is much easier to not see a clutter of connections. I'm not going to follow all of them with my finger. Even if they are there, I'll still just search for all the places where the signal of interest goes. -
If there are a clutter of connections, then the schematic has not been well drawn.
We must agree to differ. -
If there are a clutter of connections, then the schematic has not been well drawn.
We must agree to differ.
Cluttered connections cannot be avoided with some circuits/topologies. It is not simply a matter of layout, it is inherent in the connectivity. Not my bag but I think the mathematicians actually can classify networks in ways that demonstrate these differences. -
Ok, so I went back, and got rid of all the boxes. I used the Vcc and common ground symbols to eliminate wire-crossing as much as possible. I've rotated the SN754410 so that I didn't have to snake the X-axis motor signals around the bottom to get to the right side of the screen. I've also turned off the visible grid, and added a "no-connection" symbol to the unused pin on the trim pot.
Better? worse?
As a test of whether the schematic is able to convey the purpose of the circuit, can anyone guess what I'm trying to achieve with this circuit? Do you think it will work?
Thanks again for all of the input. It was very interesting to read all of the different PoVs on this subject.
Dave
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Better. But if VCC1 and VCC2 are connected, then why such complicated way to show this? Just put C1, C2 and C3 on the same level.
I would show R4 and R5 connected to VCC separately. Now it looks like there is some purpose for them to be connected to other pins of the IC.
IC symbol is drawn in a really weird way, which makes schematic capture more complicated than it needs to be. Bypass caps are least important for understaning of the functions, yet they are smack in the middle. Eliminate the whole block and move it outside.
There is also no need for all that white space on the right.
It looks like some sort of self balancing platform maybe? If the intent to have feedback-based system, then I'd say it will not work. -
Sometimes combinatorial interconnects are messy, and the best approach is to try to illustrate patterns.
I removed the power wiring and just used a node name. The op amp only needs power once, not in every unit.
I removed the decoupling and put it aside with a note explaining which part it's for.
The SN754410 got a custom component that better suits the schematic.
The motor output diodes were arranged in a pattern (again, for illustration).
The references don't match yours... I'm not THAT OCD.
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That's great!
But if we are going for perfection, why not align comparators vertically? -
Ok, so I went back, and got rid of all the boxes. I used the Vcc and common ground symbols to eliminate wire-crossing as much as possible. I've rotated the SN754410 so that I didn't have to snake the X-axis motor signals around the bottom to get to the right side of the screen. I've also turned off the visible grid, and added a "no-connection" symbol to the unused pin on the trim pot.
Better? worse?
Usable.
Personally I would connect R3's "loose" end to the wiper, to minimise noise pickup. Using opamps as comparators can have surprising results, e.g. phase reversal.
The most important parts are the sensor inputs and motor outputs, so they should be on the far left and far right. The pots can then be nearer the comparators.
Power connector is given too much prominence; it can be confined to a corner somewhere, together with the board-level bulk decoupling capacitors. It is acceptable to not connect those with wires to each IC's power supply pins, but simply to use named nets.
U2's orientation is strange. Ideally rotate CW 90degrees, move the three inputs to the left and have the two outputs to the right, with the A inputs/outputs in the top half and the B inputs/outputs in the bottom half. That will emphasise the signal flow and that there are two identical sub-circuits.