Hello,
I work since 4 weeks with Circuitstudio and I have some difficulties with the Design rules in Circuitstudio.
1) clearance between copper and pcb-edges:
Until now I have not found a rule to define a clearance between copper traces (and copper-polygon-fills) and board-outline layer.
As a workaround I copy the board shape additionally to the keepout-layer and define a clearance-rule copper<->keepout.
Kind of works, but I must not forget this step and its also additionally work.
Have I to live with the workaround or is there another/better rule/approach?
2) clearance copper - drilled holes
This is an advanced problem of nr.1 All traces need a minimum clearance to all drilled (unplated) holes and milled slots (depends on pcb-manufacturer, my minimum is 0.3mm). The keepout-layer from problem 1 (generated with "create primitives from board shape") doesn't include the holes/milling slots, so the defined clearance-rule (from problem 1) can't see the holes and doesn't see a violation if the traces are running straight without space along the holes. Can I define a rule, which detects this sort of failure?
As a workaround I will use holes and manual add concentrical keepout-circle. But this is error-prone, if I change the hole (either diameter an/or position) I will have to make identical changes to the keepout-circle.
3) minimum trace width
The appended picture shows a problem with a minimum copper width. The net connects to the pad only with a very small edge, but none of the design-rules catches this event. Neither the "unrouted" nor the "minimum trackwidth" - rules are complaining at this picture. Is there a rule which marks this picture as failure?
Thanks in advance, Maik Freitag