I'm working on some designs involving coils wound on a PCB. In the schematic editor each coil is just one line between the parts which each connect to the coil's ends, in the layout editor I've created the actual coil shapes. I designed the coil shape externally with deliberately pretty conservative spacing (0.4mm spacing between centre lines in design, then importing with a setting of a 0.2mm trace centred on the imported lines, should leave a 0.2mm gap) and imported as a dxf before assigning the relevant name to it.
In theory the coil is perfectly correct but...
I'd like to be able to use the design rule functionality to automatically check that there isn't a short circuit within the coil structure , such as the presence of a parallel path within it, something like two traces coming too close together (clearance error) that would lead to manufacturing leaing a short which would let a flowing current mostly skip going through the actual coil and take a shorter route instead.
But eagle does clearance checks only between traces with different names?
If I do any drawing of extra traces on to, or adjusting, of the coil traces I am not stopped rom running a trace which would short the coil, because eagle just sees each part of the coil as one single named net.
Is there any way to check automatically, rather than just visually going over the shape, for clearance errors between the "opposite ends of" (or rather any points widely separated along) a trace of the same name? As the coil shaped trace has a single name and serves as the only path between the component pads at its opposite ends I think the DRC is already fully able to check for open-ciruit (airwire) errors.
My Eagle version is from just pre-autodesk.
Thanks
I can't imagine any DRC complaining that some track is connected to itself. Seems to be a bit of a niche requirement.
However, could you (temporarily as a check) do a fill of the space in the coil with some other net. Arrange the clearance so you should get what amounts to a thin line all the way round, and then you can use DRC to check for islands in that fill - any island would indicate the test fill has been squeezed by the coil net getting too close to itself.
I guess you could setup the component and footprint so each turn of the coil is a separate net using net-ties.
But it sounds like a lot of work.
Can't think of any other way off the top of my head.
Ditto PlainName.
Post a zipped file of your schematic and board. Awhile back, you mentioned importing geometry and converting it to signal without any problem. So far as I know, the two circled tools (attachment) are not the same. Sometimes, they appear to be the same, but they are not. I am only familiar with version 7.x. Please name the actual version you are using.