Advantages with 4 layers without blind/burried vias?

• Advantages with 4 layers without blind/burried vias?
  Posted by okw on 26 Apr, 2023 18:31
• I see cheap manufacturers offer 4 layer boards very cheap, but without blind or burried vias.
  In JLCPCBs DRC file, they've only set up 1-16 (top-bot) layer vias.
  If I can't access the middle ones, why do I need them (except shielding the bottom from top layer)?
  Or can I set up vias from top (1) to middle-top (2), and bot (16) to middle-bottom (15)? So I can reach 1-2 without problems (or excessive tooling cost)? And if I want to reach 1-15, i need to go 1-16, then 16-15?
• #1 Reply
  Posted by tszaboo on 26 Apr, 2023 18:37
• You can reach much higher density without blind vias, just try it. You have 2 times the space for routing.
  Normally the so-called stackup is: Routing - GND - Power supply - routing. It's better for EMC, and even if you don't care about that stuff, it will work on higher frequency better.
• #2 Reply
  Posted by thm_w on 26 Apr, 2023 20:27
• You can access the middle layers. The via is drilled through (1-4), then you connect a trace to it wherever you want. You can have trace on layer 1 go to layer 2, or 3, etc.
  
  Look at the "through hole" image here: https://www.pcbgogo.com/Blog/PCB_Vias__Something_You_Need_To_Know.html
• #3 Reply
  Posted by Doctorandus_P on 27 Apr, 2023 07:55
• Both blind and buried via's are quite special, and they require separate process steps (which also costs extra, so you won't get them for rock bottom prices) But that still leaves "normal" / "regular" via's. A regular via is made by drilling a hole through the whole PCB, and then plating the hole on the inside. So such a via always reaches all layers of the PCB, but of course it does not have to have a copper track connected at each layer. If you're interested, go watch some youtube video's about PCB manufacturing.
• #4 Reply
  Posted by mikeselectricstuff on 27 Apr, 2023 08:17
• Quote from: okw on 26 Apr, 2023 18:31

  I see cheap manufacturers offer 4 layer boards very cheap, but without blind or burried vias.
  In JLCPCBs DRC file, they've only set up 1-16 (top-bot) layer vias.
  If I can't access the middle ones, why do I need them (except shielding the bottom from top layer)?
  

  You misunderstand - through vias access all copper layers, not just the outer ones.
  
• #5 Reply
  Posted by Warhawk on 04 May, 2023 07:39
• Quote from: okw on 26 Apr, 2023 18:31

  I see cheap manufacturers offer 4 layer boards very cheap, but without blind or burried vias.
  In JLCPCBs DRC file, they've only set up 1-16 (top-bot) layer vias.
  If I can't access the middle ones, why do I need them (except shielding the bottom from top layer)?
  Or can I set up vias from top (1) to middle-top (2), and bot (16) to middle-bottom (15)? So I can reach 1-2 without problems (or excessive tooling cost)? And if I want to reach 1-15, i need to go 1-16, then 16-15?
  

  
  I use 4-layer PCBs quite often and without buried/blid vias. I use one middle layer for the solid ground plane. The other one for power. Top and bottom for signals. You achieve very good density with access to most/all important signals for debugging. My designs scale up to hundreds of components, typ. 0402 +QFNs etc. I hope this helps.
• #6 Reply
  Posted by Psi on 04 May, 2023 08:13
• Quote from: mikeselectricstuff on 27 Apr, 2023 08:17

  Quote from: okw on 26 Apr, 2023 18:31

  I see cheap manufacturers offer 4 layer boards very cheap, but without blind or burried vias.
  In JLCPCBs DRC file, they've only set up 1-16 (top-bot) layer vias.
  If I can't access the middle ones, why do I need them (except shielding the bottom from top layer)?
  

  You misunderstand - through vias access all copper layers, not just the outer ones.
  

  
  yep. You can choose which layers the through-via connects to by if the drill passes through copper on each layer, or not.
  If the drill passes through copper the plating process will connect it to that copper layer.
  
  Think of blind or burred via's as just a hole that does not go all the way through the PCB.
  
  The only thing blind or buried via's gets you is the ability to combine both a via and a SMT pad in the same location.
  If you have lots of via's it limits you where you can put SMT pads and stuff because you have to avoid all the holes in the PCB.
  But if you can change a via to blind (one sided) you can regain that space on either top or bottom.
  If you can change a via to buried (inside only) you regain the area on both top and bottom layers of the via's location.
  
  Normally you have zero blind or burred via's unless you have
  - a BGA and you cant fan-out the tracks without using blind or burred vias.
  OR
  - a super high density pcb with components all packed super tight together and don't have room for holes on the top and/or bottom layers.
  
  Any blind or burred via's puts your board cost up, it doesn't really matter how many you have (within reason) because the price increase is just for the extra process and once you need that process it's free to add more of them.
  So if you need 1 you might as well use them everywhere to tidy up your PCB.
• #7 Reply
  Posted by okw on 14 May, 2023 23:22
• I think I was over-complicating things. I leave the via pairs "through 1-16" as default, then define polygons for GND and VCC on layers 2 and 15.
  Then I just use vias as I've always done with 2 layers, and Eagle will automatically connect these to their respective nets?
  I thought I had to via them manually (select via pairs) to their correct layers (which would be a pain and a lot of work).
  
  Second question, I saw some Autodesk video where he continues to route after he via into an internal layer. I have a small portion of the board (5%) which is 12V, rest is 3.3V. Would it be good practice to not draw the VCC polygon where the 12V is, and then route the 12V manually in the VCC layer, or even create a 12V polygon instead of 3.3V in this part of the board?
• #8 Reply
  Posted by thm_w on 15 May, 2023 20:43
• Quote from: okw on 14 May, 2023 23:22

  I think I was over-complicating things. I leave the via pairs "through 1-16" as default, then define polygons for GND and VCC on layers 2 and 15.
  Then I just use vias as I've always done with 2 layers, and Eagle will automatically connect these to their respective nets?
  I thought I had to via them manually (select via pairs) to their correct layers (which would be a pain and a lot of work).

  
  I don't use Eagle but thats usually how it works yes. You don't have to select anything manually, unless it didn't pick up which net you want the via to be in which case you can click on the via and assign it a net.
  
  

  Quote

  Second question, I saw some Autodesk video where he continues to route after he via into an internal layer. I have a small portion of the board (5%) which is 12V, rest is 3.3V. Would it be good practice to not draw the VCC polygon where the 12V is, and then route the 12V manually in the VCC layer, or even create a 12V polygon instead of 3.3V in this part of the board?

  
  Normally you'd have the polygon everywhere, draw your 12V trace, then the polygon will be repoured to make space for that trace you've drawn.
  You don't need to selectively draw. If you had a reason for extra clearance, you'd create a larger clearance rule between 12V and 3V. But since the voltages are so low it shouldn't be needed.
• #9 Reply
  Posted by tszaboo on 16 May, 2023 12:46
• Quote from: okw on 14 May, 2023 23:22

  I think I was over-complicating things. I leave the via pairs "through 1-16" as default, then define polygons for GND and VCC on layers 2 and 15.
  Then I just use vias as I've always done with 2 layers, and Eagle will automatically connect these to their respective nets?
  I thought I had to via them manually (select via pairs) to their correct layers (which would be a pain and a lot of work).
  
  Second question, I saw some Autodesk video where he continues to route after he via into an internal layer. I have a small portion of the board (5%) which is 12V, rest is 3.3V. Would it be good practice to not draw the VCC polygon where the 12V is, and then route the 12V manually in the VCC layer, or even create a 12V polygon instead of 3.3V in this part of the board?
  

  You can do either. They are acceptable EMC and board design wise. Or if 12v is just the input, might as well route it with regular tracks. Best practice is to keep GND plane complete though.
• #10 Reply
  Posted by RedLion on 24 May, 2023 15:17
• If you have something fast switching on the 12V level, I would probably try to contain it to an area and give it a power plane.
  Same if you have some very high currrents and you're worried about impedance or heating. Keeps the traces short and sweet.
  If the 12V is mainly doing slow stuff and supply, you can just run it as a trace to where you need it.
  
  Most of what we do in the automotive sector is done on 4 layers with standard vias, 6 layers is usually too expensive.
  Given the sheer of different supply nets, high current traces and the like, layer 3 ends up being quite the mosaic.
  Albeit in inverters, more often than not we have to compromise on proper power planes since we route on layer 3 as well. Still works somehow.
• #11 Reply
  Posted by okw on 24 May, 2023 18:37
• I have a buck (AP64352Q) with programmable switching frequency (100kHz to 2.2MHz). Seems i need to move higher than 480kHz to get the current I need out of it (~500mA), so I'll go with 500kHz.
  Besides that, there is no switching or high currents.
  I was thinking to make a small polygon for an internal isolated ground plane under the automotive 12V power input (tvs, reverse polarity, overcurrent, overvoltage, etc). Then connect this at a single point to the rest of the internal ground plane. Good idea?
  Something to watch out for?