I had to modify an older design that was put together years ago.
It seems that all of the power and ground pins on chips were not part of the individual component's schematic model and required opening the component's Properties window and assigning the nets under "SigPins". This is in PADs.
Was this ever a common practice? Sure, it can make the schematic look a little cleaner but if a technician were ever to look at the schematic to diagnose an RMA, how would they know what pins are connected to what rails?
It just seems like a really odd design and dangerous documentation choice. Or am I off-base and this is common?
I think it's just a historical feature. It was supposed to be used with boards containing dozens of TTL logic. They all ran from the same power rail and had the power pins in the same place for each package, so there was no need to spell it out for the tech.
Seen it with FPGAs where you have dozens of ground balls, that are basically uninteresting. Same thing for the dozen or so core power balls, I mean who needs that stuff cluttering up a schematic?
It can be dangerous for sure, but is a useful tool in the right place.
Regards, Dan.
One of my pet hates in schematics is having information that's essential to the operation of the design, but which can't be seen on a hard copy.
Hidden power pins are one example of this. Hiding power pins completely is a heinous crime; if you don't want them cluttering up a part of the design, split them out into a separate power & ground symbol, and put them on another page together with their decoupling caps.
Related crimes include calling a power net something like "VCC" instead of "+3V3", which tells the reader immediately what the supply rail voltage should be. The designer needs this information to be sure a chip is actually connected to the correct supply rail, and a technician may need the same information later on to tell whether or not a given supply is working correctly. Calling it something vague instead of stating the voltage explicitly is only OK if the supply voltage itself is variable, like the output of a solar panel, or a voltage which is altered at run time to trade CPU speed vs power dissipation.
There's a special circle in hell for designers who give the same net different names on different pages of the schematic, and expect the reader to navigate endlessly up and down their design's unnecessary hierarchy to keep track of which net is which.
Yes it did used to be common practice. particularly, as said above, with logic families like 74 series TTL.
The problem came when wanted to use a different supply voltage, or maybe a switched version of VCC so half the circuit could be powered down in a low power application.
You ended up, as in our case, with several versions of the same part in the library, one with visible supply pins and one without. I caused chaos with the MRP system. It should never have been allowed
There's a special circle in hell for designers who give the same net different names on different pages of the schematic, and expect the reader to navigate endlessly up and down their design's unnecessary hierarchy to keep track of which net is which.
I agree totally but then a good CAD system should not allow this to happen anyway. Although someone will always find a way round it like change the name after a connector maybe.
It's not really something that the CAD system can do much about. The problem almost (but not quite) always stems from a desire to make a design hierarchical, even when there's no practical benefit from doing so.
Hierarchy is fine if, say, a design has multiple ports or channels. Then, of course it makes sense to draw the repeated components as a single block, and the net names within the block automatically get a suffix indicating which instance of the block they belong to. In this case the names are consistent, predictable, and descriptive. No problem.
I can also see the benefit if a design is hugely complicated, and/or includes really substantial portions which are taken from other schematics. In that case, keeping them as a tried and tested, separate entity makes sense.
However... I do see quite a few schematics where the designer has tried to follow some unwritten "good practice" manual, and has partitioned the schematic into functional blocks, where each of them is only a page or two, and the blocks are joined together by a top level design. The theory is that you get an accurate block diagram "for free".
Unfortunately, what it really means is the same net can get three different names: one at the source, one at the top level where the blocks are joined, and one at the destination. (Think "CLK_20M_LVCMOS" becomes "CLK_20_LVCMOS" becomes "CPU_CLK").
It's valid, but lazy. If you want a block diagram, draw one. A 10 page schematic doesn't need, or benefit from, being chopped into chunks.