I think in AD17+ they added blind holes as an option, without having to set up drill layer pairs? I haven't touched it so I'm not sure.
Otherwise, the canonical way to represent them, in Altium, I think, would be to set inner layers, at the depth desired, and use vias on those layer pairs. You would then add a fab note that the inner layers are not to be fabbed, that they are intentionally empty, and that the design is to be fabricated as a 2-layer design with blind holes of specified depth.
No, I don't think there's a streamlined way to do this. It would be nice to generate extra fab outputs, say a drill file for thru holes, a separate one for blind holes including correct depth commands, and so on; and you can probably do this, but how it's going to be represented in the EDA files, and if there are unnecessary side effects (like including layers you don't want), dunno.
Ed: and yeah, for a pin like that, you'd normally have a thru hole, and that's that. Mind that the minimum depth, to the shoulder of the hole (the drill will have a conical tip, or if an end mill is used, it will have some corner radius), has to be at least the maximum length of that pin. With a tolerance of maybe 5 or 10 thou depthwise (don't expect miracles -- do check with the fab to see what their capability is), the typical hole will likely break through the other side of the board anyway. If you need a sealed hole, consider using the next size thicker PCB (typically around 0.093" / 2.4mm?), or a soldered pin.
Tim