While curious about how your 32bit DAC works and looking at the code and SD DAC whitepaper you refer to, let me kindly ask you - does it mean you modulate (within a periodic ISR) a 16bit PWM duty with the sigma delta modulator's 1bit output?
Ok, the LSB of the 15.2bit 10kHz PWM "duty" is resolved by the 16.8bit SD modulation, basically. What is the SD's isr() frequency (or period)? [I can see there 3.13us in the comment but it does not fit into my current understanding of the process..]
For the "noise" measurement, I'm getting standard deviations of about 5 uV on a 34401A with 50 samples with NPLC=100 (60Hz). Is this good or bad?
Another idea I had was if it's a good idea to use the LM399 without its heater.
Jitter continues to be an issue. The period of the 100us cycle has a P-P jitter of about 450ns.
There are a number of microcontrollers and digital signal controllers that offer a "High Resolution Timer" in the form of a 16-bit PWM followed by a 32-stage selectable delay line. Some of these control the accuracy of the delay line transparently in hardware, while most of them require firmware support to do this.
As the LM399 is only stable (over the 2 nd year) to maybe 5 ppm, there is not much sense in an adjustment much finer than 20 Bits. So the 22 Bits of the original project is fine.
One point possibly worth a look would be the ADG419 switch. It is relatively slow and might cause some jitter. One might consider a faster switch, maybe even 74HC4053 - it's faster but would need a kind of +-5 V supply.
The '334 hires pwm is with 16bits resolution only. I would be happy to know more chips with 16bit pwm at 4.6GHz pwm clock, indeed.
You can connect an external AND-OR gate (SN74LVC1G0832) to the PWM output and two extra GPIO pins. You set up an interrupt on the positive edge of the PWM and another on the negative edge. These two interrupt routines control a 'PWM-FORCE' signal (which goes to the OR gate input) and a 'PWM-ENABLE' signal (which goes to one of the AND inputs)-- with the original PWM going to the remaining input of the AND gate. This can provide an extra 4-bits of resolution, where the PWM controls both the positive and negative edges (and the force and enable signals are not that critical). This can be (practically) a 25-bit DAC without any dithering at all. If you want even more resolution, you can add (maybe) 3 more bits on the bottom, that dither the 25th bit, providing 28-bits total-- and the code dependent low frequency artifacts will be very small.
Get it now?
You can connect an external AND-OR gate (SN74LVC1G0832) to the PWM output and two extra GPIO pins. You set up an interrupt on the positive edge of the PWM and another on the negative edge. These two interrupt routines control a 'PWM-FORCE' signal (which goes to the OR gate input) and a 'PWM-ENABLE' signal (which goes to one of the AND inputs)-- with the original PWM going to the remaining input of the AND gate. This can provide an extra 4-bits of resolution, where the PWM controls both the positive and negative edges (and the force and enable signals are not that critical). This can be (practically) a 25-bit DAC without any dithering at all. If you want even more resolution, you can add (maybe) 3 more bits on the bottom, that dither the 25th bit, providing 28-bits total-- and the code dependent low frequency artifacts will be very small.
Get it now?
I think I see what you're suggesting.
I think we need to run the final PWM at between 5 and 30 kHz to allow for a reasonable analog filter. The extra bits you output let you construct a few extra MSB that are controlled in software. This also allows the internal timer clock/DLL/whatever to be run at a speed (providing a better time-resolution).
However, I don't see how you could add many more bits without going to much lower resultant PWM frequencies. For example with the STM32F334, the internal PWM period could be up to about 62 kHz (with f_HRTIM=128 MHz*32, 16 bit), and add three extra bits to get a final PWM rate of 7.75 kHz (without dithering). I'm not sure that it's a good idea to go any slower than that.
During my testing of the 'F334, I'm now reading about 53 mA. No matter what I do (other than turning off the HRTIM unit), I can't get the current draw to significantly decrease. I've tried, for example, disabling the unused subtimers and setting their clock dividers to the most divided.
I did also order another dev board today, a TI launchxl-f28027. I'll report on how its PWM generator performs (and current consumption).
A filter for 137Hz is EASY, since you would be filtering the output of the Delta-Sigma integrator, which will have a rather small triangle wave with some spikes due to the finite slew rate of the op-amp. Just a 3-pole filter would do it, and the 137Hz remaining would be well below the noise floor.
What is the -3dB of your 2pole SK filter?
Is the value of R7 ok?