You probably will be able to download ISE 14.7 a century from now. It still will be available and if you have a computer that will run a 100 year old OS, you will be able to fire it up. There will not be anybody to call up when you have a question or find a bug.
But I would still recommend starting with a legacy device and the legacy softward if tutorials were of any concern.
As much as Xilinx would want it ISE isn't going to be obsolete for the next couple of years. There is still too much not working right in Vivado.
Hi
I've seen this process before. As much as the new super version has issues (they always have issues) ... they do go ahead and kill the older version. I'm not in any way saying that's right. It is what happens. If you get a couple of years of overlap that's better than the way some places do it. They *have* to get rid of the cost of support on the older version. A number of people's bonus plans depend on it. That's what makes it happen.
Bob
I think Xilinx is pretty up-front about the fact they no longer support ISE but what are they going to do, leave millions of projects with no support whatsoever? That's not a winning strategy.
Their view is that they will leave 14.7 out there to support the devices in the field and move on to Vivado with just the slightest overlap in devices. I don't see 14.7 going away, ever...
If they did kill off 14.7, how would they redefine 'field upgradeable'? I think having a copy of the old version 10.x is pretty handy as well. I still have Spartan 2 devices to program.
Hi
You probably will be able to download ISE 14.7 a century from now. It still will be available and if you have a computer that will run a 100 year old OS, you will be able to fire it up. There will not be anybody to call up when you have a question or find a bug. The latest and best timing info will be in other programs (even for the old parts). That is likely OK for a project you did 100 years ago and simply want to do a small tweak on. Available is not the same as supported ....
Bob
True enough. The thing is, Xilinx has no intention of supporting legacy devices with Vivado. Even chips as new as the Spartan 6 aren't supported in Vivado. Nor do I expect them to ever incorporate the legacy devices. They have a plan for moving forward and it works for me. I can use the old software to support my older projects and I can use the new software with my newer projects. But I would still recommend starting with a legacy device and the legacy softward if tutorials were of any concern.
If not, the Arty Artix 7 board is pretty nice as is the Digilent Basys 3. In fact, the Artix would handle this job pretty well:
http://store.digilentinc.com/arty-board-artix-7-fpga-development-board-for-makers-and-hobbyists/
Mount a little mezzanine board on top for connecting the inputs and the rest is ready to go. This board works well with Vivado.
The OP wants a shitty FPGA that samples 16 pins at 60Hz, and now it has derailed to ISE vs Vivado ...
OP: If you do not want to use iceCube2, you can try PSoC. Still more than enough for your need. But I still recommend iCE40.
The smallest iCE40LP384 does have a QFN32 package and I believe I can write code to make it a synchronized SPI IO expander for less than 30 lines.
Back up and re-read it. He wants 10 nanosecond samples. The data comes out at a 60 Hz rate. That isn't going to happen with a PSoC.
PSoC devices have DSI interface, which allows async IO input directly into PLD fabric. Maybe not 16 channels, but 8 channels is easy, and you can use 2 chips to get 16 channels.
DSI input latch can also be used with an external clock, which even further reduced PLD fabric delay mismatch.
Hi
Yup, The Trenz 725 is a Artix-7 board that can easily mount on an application specific board. That's what the OP went with. It's a pretty rational little chip with enough cool features to spend lots of time playing with.
Bob
Hi
Yup, The Trenz 725 is a Artix-7 board that can easily mount on an application specific board. That's what the OP went with. It's a pretty rational little chip with enough cool features to spend lots of time playing with.
Bob
And a JTAG programmer? I don't see an onboard USB->JTAG gadget so I suspect there needs to be something else at that JB1 header.
I like the 'stamp' format for boards. Lots and lots of IO pins.
You need 16 counters that *async* clock at 100 MHz ... not going to happen on a PSoC. All the data and "clocks" are re-done against the CPU clock. That makes it a really rotten thing for precision timing.
Data path and clocks are not synced if you do not want to do so. That's where DSI and HSIOM kicks in.
As for the counter part, who cares about relative phase shift against master clock? The OP only cares about <10ns jitter and <10ns channel skew. With async logic, it can be easily done.
PS. I'm referring to PSoC 4200 family, as I'm now working on it.
If this is a start from scratch / I know none of them sort of thing - VHDL is what I'd pick.
If this is a start from scratch / I know none of them sort of thing - VHDL is what I'd pick.
Why VHDL? Any particular reason to choose it over Verilog or SystemVerilog?
Pretty much everybody I know uses VHDL over the Verilog empire.
Pretty much everybody I know uses VHDL over the Verilog empire.
That's a quite personal (and very valid) reason to choose VHDL. Having others around you who are familiar with a language is certainly a big help, especially for beginners.
Let's assume an FPGA beginner wants to learn Verilog or VHDL, but doesn't have anyone around who knows either one. Which one would you recommend he choose? Why?
Pretty much everybody I know uses VHDL over the Verilog empire.
That's a quite personal (and very valid) reason to choose VHDL. Having others around you who are familiar with a language is certainly a big help, especially for beginners.
Let's assume an FPGA beginner wants to learn Verilog or VHDL, but doesn't have anyone around who knows either one. Which one would you recommend he choose? Why?
For what it's worth I have been using iCE40 for about three years now.
I use ISE to synthesise and simulate and then iCECube2 to get it on the chip.
I can thoroughly recommend "Advanced Digital Design with the Verilog HDL" book but it's expensive (£150). There are three words in the preface...
Simplify, Clarify and Verify
That pretty much sums it up for me - so only £50 per word
My big lesson was to only put on the FPGA that which _has_ to be there; if a micro can do it, put it in the micro. So I simplified the FPGA, clarified that it would still do the job and then verified it.
One really nice feature of the iCE40 is that there is an SPI interface which is used to write the 'image' to the device (same port is used to program the non-volatile on-board memory when you want to finalise the design), and when you are testing that can come from a local micro. Then, when the FPGA is running, those SPI pins can be used to interface to your design (pins programmed to be SPI of the FPGA design) via your local micro. For quite a lot of things it's like having an FPGA with a micro on board. One thing I really like is using the SPI as an I2C "global" interface. The LE line becomes SPI / I2C select so when low it's an SPI port, high I2C. The SPI clock becomes SCL and data send is MOSI, the data return being MISO. You can then connect a load of I2C devices to different pins on the FPGA (to save PCB layout headaches) and just AND all the SDA pins when LE is high
The other thing is, I have been clocking the iCE40 with a CDCE925 which will go up to 230MHz (the CDCE that is) and whilst I have only been running it at a tad under 200MHz it is completely solid. That's after temperature cycling and so on. That allows you to use an ARM with an SPI running at 42Mb/s which is pretty cool.
Needless to say I am a fan of iCE40
I picked up an iCEstick two years ago learn FPGAs with and have yet to do anything with it. Are there any good guides or tutorials for working with iCECube2 you could recommend? I've found lots of good resources on VHDL and Verilog, as well as some decent tutorials for ISE and Quartus, but not so much for iCECube2.
When you have a need to accomplish something, you will learn it automatically .
True enough. The thing is, Xilinx has no intention of supporting legacy devices with Vivado. Even chips as new as the Spartan 6 aren't supported in Vivado. Nor do I expect them to ever incorporate the legacy devices. They have a plan for moving forward and it works for me. I can use the old software to support my older projects and I can use the new software with my newer projects. But I would still recommend starting with a legacy device and the legacy softward if tutorials were of any concern.
If not, the Arty Artix 7 board is pretty nice as is the Digilent Basys 3. In fact, the Artix would handle this job pretty well:
http://store.digilentinc.com/arty-board-artix-7-fpga-development-board-for-makers-and-hobbyists/
Mount a little mezzanine board on top for connecting the inputs and the rest is ready to go. This board works well with Vivado.