Figure 41. Chain Mode with Busy Indicator Connection Diagram
https://www.analog.com/media/en/technical-documentation/data-sheets/ad7980.pdf
May be 1 or 2 SPI would be sufficient.
Figure 41. Chain Mode with Busy Indicator Connection Diagram
https://www.analog.com/media/en/technical-documentation/data-sheets/ad7980.pdf
May be 1 or 2 SPI would be sufficient.
Even 1 channel would be fine because the conversion for all units is controlled by a single digital output from the uC. There are no 'programming' commands so chaining the devices together makes all the sense in the world.
I've taken on a project that out of my comfort zone and i have trouble selecting a microcontroller that can handle that data throughput.
issue:
4x 16bit ADC @ 1MSPS (ad7980, or similar. using 3-wire spi)
Continues sampling, into buffers (4* 640 data points) threshold trigger on 1 buffer.
Then offloading to other micro (open to changing that) , for data processing.
Figure 41. Chain Mode with Busy Indicator Connection Diagram
https://www.analog.com/media/en/technical-documentation/data-sheets/ad7980.pdf
May be 1 or 2 SPI would be sufficient.
Even 1 channel would be fine because the conversion for all units is controlled by a single digital output from the uC. There are no 'programming' commands so chaining the devices together makes all the sense in the world.I was thinking two SPI if OP needs 1 MHz sampling rate sharp, than SPI clock jumps up >64 MHz, and I don't know any uCPU that could handle such high rate. Wait, seems stm32H7 could get 150 Mb/s, but non of F3, F4 or F7.
While we're on the subject, can an IO line really toggle at 1 MHz to start the samples?
What is the limit of the uC SPI clock.
As it turns out, the AD7980 has a cycle time of 1.2 uS or 833 kHz. It can't do 1 Msps. See tcyc on page 6 of the datasheet.
I've taken on a project that out of my comfort zone and i have trouble selecting a microcontroller that can handle that data throughput.
issue:
4x 16bit ADC @ 1MSPS (ad7980, or similar. using 3-wire spi)
Continues sampling, into buffers (4* 640 data points) threshold trigger on 1 buffer.
Then offloading to other micro (open to changing that) , for data processing.
Where does all this ultimately end up ? 4 * 640 points, sounds like a simple scope ?
As already mentioned, 1 MSPS is not particularly fast, so a MCU's ADC's might get close.
If you do need external ADCs for noise/speed/location reasons, then a small FPGA with good RAM may be ideal for you.
The Lattice iCE40UP5K-SG48I has a decent 128kBytes SRAM, and comes in a QFN48 package - it could do any manner of SPI-ADC buffering.
google finds
More standard breakout board ICE40UP5K-B-EVN
More compact version HM01B0-UPD-EVN
Both boards include FT2232H, so you have a 12MBd PC link, if you need that too.
I've taken on a project that out of my comfort zone and i have trouble selecting a microcontroller that can handle that data throughput.
Figure 41. Chain Mode with Busy Indicator Connection Diagram
https://www.analog.com/media/en/technical-documentation/data-sheets/ad7980.pdf
May be 1 or 2 SPI would be sufficient.
Even 1 channel would be fine because the conversion for all units is controlled by a single digital output from the uC. There are no 'programming' commands so chaining the devices together makes all the sense in the world.I was thinking two SPI if OP needs 1 MHz sampling rate sharp, than SPI clock jumps up >64 MHz, and I don't know any uCPU that could handle such high rate. Wait, seems stm32H7 could get 150 Mb/s, but non of F3, F4 or F7.
Number crunching will clearly be required. The maximum clock rate will just about handle 4 devices on one SPI channel. But... What about the rest of the latency? DMA requests, SPI overhead, framing requirements and so on. While we're on the subject, can an IO line really toggle at 1 MHz to start the samples? Is that signal going to come from a timer? We have just 1 uS to start the conversion What is the limit of the uC SPI clock.
As it turns out, the AD7980 has a cycle time of 1.2 uS or 833 kHz. It can't do 1 Msps. See tcyc on page 6 of the datasheet.
I like the idea of a single conversion start signal for multiple ADCs. Bringing the data in via 4 separate SPI gadgets makes sense and using 4 DMA channels also makes sense. What I don't know is the maximum data rate for the DMA channels (assuming all 4 go ready at the same time).
As I said, somebody is going to need to do some number crunching.
One thing that hasn't been discussed is whether the data is sampled in burst mode where 640 samples are taken and the process stops for some long period of time or is the sampling continuous and attempting to capture 4 @ 640 samples for some large number of iterations. This matters with the USB->Serial approach if the data capture is done in an FPGA. I don't know what the maximum throughput is for the USB->Serial channel. More numbers...
I think I would lay the timing out in a spreadsheet along one line. Use a column for each step of the process. Finally, add up the row and see if the 1 Msps requirement is met.
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I like the idea of a single conversion start signal for multiple ADCs. Bringing the data in via 4 separate SPI gadgets makes sense and using 4 DMA channels also makes sense. What I don't know is the maximum data rate for the DMA channels (assuming all 4 go ready at the same time).
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I think I would lay the timing out in a spreadsheet along one line. Use a column for each step of the process. Finally, add up the row and see if the 1 Msps requirement is met.
Hmm the "featured" Throughput: 1 MSPS, is kinda misleading.
I've taken on a project that out of my comfort zone and i have trouble selecting a microcontroller that can handle that data throughput.
issue:
4x 16bit ADC @ 1MSPS (ad7980, or similar. using 3-wire spi)
Continues sampling, into buffers (4* 640 data points) threshold trigger on 1 buffer.
Then offloading to other micro (open to changing that) , for data processing.
Where does all this ultimately end up ? 4 * 640 points, sounds like a simple scope ?
As already mentioned, 1 MSPS is not particularly fast, so a MCU's ADC's might get close.
If you do need external ADCs for noise/speed/location reasons, then a small FPGA with good RAM may be ideal for you.
The Lattice iCE40UP5K-SG48I has a decent 128kBytes SRAM, and comes in a QFN48 package - it could do any manner of SPI-ADC buffering.
google finds
More standard breakout board ICE40UP5K-B-EVN
More compact version HM01B0-UPD-EVN
Both boards include FT2232H, so you have a 12MBd PC link, if you need that too.
In the end the buffers are used for cross correlation and then a algorithm that does dispensation compensation and localisation.
But the idea is that this processing can happen at a later time, and the buffered data can be stored on a sd-card.
The external ADC where chosen for noise.
Actually just found that the STMM32H750 value line series has 3 of the 3.6MSPS 16-bit adc's. And they can also differential or single ended capable.
Along with 1MB of ram, it does have comparatively small flash of 128KB though.
And it's in stock at digikey for $7.32@1qty and is less than $4.66@540qty
That is less than 1/3 the price of a single AD7980 (on digikey for $15.73@500qty and $19.98@1qty.
Seems like a bit of a no-brainer to me unless I am missing something..?
Please correct me if I am wrong
As it turns out, the AD7980 has a cycle time of 1.2 uS or 833 kHz. It can't do 1 Msps. See tcyc on page 6 of the datasheet.
Actually just found that the STMM32H750 value line series has 3 of the 3.6MSPS 16-bit adc's. And they can also differential or single ended capable.
Along with 1MB of ram, it does have comparatively small flash of 128KB though.
And it's in stock at digikey for $7.32@1qty and is less than $4.66@540qty
That is less than 1/3 the price of a single AD7980 (on digikey for $15.73@500qty and $19.98@1qty.
Seems like a bit of a no-brainer to me unless I am missing something..?
Please correct me if I am wrong
Ok, I don't mind correcting you
The STM32H7 has 12-bit ADCs. Higher resolutions are achieved by oversampling which is done in H/W by averaging. To get 16 bit resolution you need to average at least 16 samples so the maximum sampling rate would be 225kSPS.
To match the AD7980 noise performance you might need to average rather more than 16 samples depending on the noise characteristics of the STM32H7 ADC (which is only specified at 12bits and 2MSPS so presumably it will be worse at 3.6MSPS). If the noise is correlated to any degree then the amount of improvement with oversampling will be less than predicted by the usual 1 bit improvement in noise performance by averaging 4 samples (ie. 4X oversampling).
Please correct me if I am wrong
Ok, I don't mind correcting you
The STM32H7 has 12-bit ADCs. Higher resolutions are achieved by oversampling which is done in H/W by averaging.
To obtain 16 bits of resolution, you need to downsample by >= 256x, not 16x. Each factor of four gives you one bit, in the best case, if the noise is white and the signal is sufficiently dithered.
Also, the simple averaging provided by most MCUs is not really proper downsampling; it is a very loose low-pass filter (sinc^1) followed by the decimate-by-N stage. Better would be something like the DFSDM peripheral on some STM32 MCUs.
Notice that the moving average filter has no overshoot. This makes it useful in signal processing applications where random white noise must be filtered but pulse response reserved. Of all the possible linear filters that could be used, the moving average produces the lowest noise for a given edge sharpness.
They are specified as 16 bits at 3.6MSPS with noise performance of 13.5 ENOBs at 2MSPS. So oversampling will be required to match the AD7980 noise performance.