There is not any real RISC V hardware. Who would invest into making a commercial system? The best you will probably see in coming years is the same GCC/Eclipse + commercial support.
Are there any commercial tools for the RISC-V architecture (i.e. where a licence includes full support), or is the Eclipse/GCC toolchain the only option at present?
Thanks, that's pretty much what I expected. We want to get custom ASIC designed and ideally wanted a Cortex M4 core in it since we have plenty of experience and all the tools, but the licensing and royalty cost is a little eye watering but doable. ASIC vendor suggested we consider using RISC-V, so just looking at the options.
Thanks, that's pretty much what I expected. We want to get custom ASIC designed and ideally wanted a Cortex M4 core in it since we have plenty of experience and all the tools, but the licensing and royalty cost is a little eye watering but doable. ASIC vendor suggested we consider using RISC-V, so just looking at the options.
Are there any commercial tools for the RISC-V architecture (i.e. where a licence includes full support), or is the Eclipse/GCC toolchain the only option at present?
What kind of support do you want? gcc and eclipse are mature technology and unlikely to be very broken compared to hacked-up proprietary tools, so the main support needed seems to be beginner hand-holding. I don't use eclipse, but gcc, gdb, openocd work fine for me.
Interesting. Who is the ASIC vendor?
Making custom ASICs with a RISC-V core in the Cortex M4 class is exactly the thing SiFive has already demonstrated they can do -- and want to do. Contact them if you haven't already.
That's so cool, what sort of prices does ARM want for cortex M4?
We've not had an official quote yet, but my research suggests around $200k for licensing, no idea on royalties. It's relatively low compared to the total cost of developing the entire thing, but needs to be traded off against possible risks and time of using an unknown (to us) architecture and unsupported tools.
I have nothing against GCC given it's price, and have used it for many years on personal projects. There isn't much love for Eclipse amongst the team I work with however.
gcc and eclipse are mature technology and unlikely to be very broken compared to hacked-up proprietary tools
gcc and eclipse are mature technology and unlikely to be very broken compared to hacked-up proprietary toolsOn the other hand, the RISC-V port is quite new, and there seems to still be a decent amount of bug fixing activity going on.
I'd say the biggest sticking point would be what kind of instructions you need. Plain old integer code, great, no problem. Single and double precision floating point are there too, though there isn't yet a commercially buyable core implementing them -- SiFive's U54 quad core processor due early 2018 will have DP FP.
I'd say the biggest sticking point would be what kind of instructions you need. Plain old integer code, great, no problem. Single and double precision floating point are there too, though there isn't yet a commercially buyable core implementing them -- SiFive's U54 quad core processor due early 2018 will have DP FP.
The reason we wanted the M4 core over M3 was for the FPU, so this would need to be part of the RISC-V implementation as well. I'm told the IP is available for that.
Western Digital announced that:
1) they ship over one billion processors a year, and
2) over the next several years they are switching them all to RISC-V
Some interesting developments at the 7th RISC-V Workshop Milpitas, CA, today.
Western Digital announced that:
1) they ship over one billion processors a year, and
2) over the next several years they are switching them all to RISC-V
Western Digital announced that:
1) they ship over one billion processors a year, and
2) over the next several years they are switching them all to RISC-VAre you sure they are shipping this quantity? The slide you reference seems to imply that after several years of transition they will be shipping a billion cores.
RISC-V is an open and scalable compute architecture that will enable the diversity of Big Data and Fast Data applications and workloads proliferating in core cloud data centers and in remote and mobile systems at the edge. Western Digital’s leadership role in the RISC-V initiative is significant in that it aims to accelerate the advancement of the technology and the surrounding ecosystem by transitioning its own consumption of processors – over one billion cores per year – to RISC-V.
Western Digital is engaged in active partnerships and investments in RISC-V ecosystem partners. The company recently completed a strategic investment in Esperanto Technologies, a developer of high-performance, energy-efficient computing solutions based on the open RISC-V architecture. Esperanto, which is headquartered in Mountain View, Calif., includes a seasoned team of experienced processor and software engineers with the goal of making RISC-V the architecture of choice for compute-intensive applications, such as machine learning.
“The open source movement has demonstrated to the world that innovation is maximized with a large community working toward a common goal,” said Fink. “For that reason, we are providing all of our RISC-V logic work to the community. We also encourage open collaboration among all industry participants, including our customers and partners, to help amplify and accelerate our efforts. Together we can drive data-focused innovation and ensure that RISC-V becomes the next Linux success story.”
Western Digital announced that:
1) they ship over one billion processors a year, and
2) over the next several years they are switching them all to RISC-VAre you sure they are shipping this quantity? The slide you reference seems to imply that after several years of transition they will be shipping a billion cores.
They definitely said >1b today, several billion a year by the time the transition is complete.
Do they also count multiple cores in one chip? 100M chips with 10 cores is 1B cores.