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STM32 microcontrollers, especially STM32F030
two weeks ago I saw an interesting project, STM32F + Spartan6, for a portable gaming console. -
I actually has a sort-of similar project plan: AT91SAM9260-QU + TMS320VC5509A + EP4CE15E22C8N triple-hitter with 256MB DRAM, Wi-Fi and M.2 SATA. That would be either a huge 4-layer board, or a stack of PC104 style boards. The ARM processor is the system master here, I need to cook up something akin to U-Boot + UEFI in the XIP NOR Flash so the actual operating system can be located in the SATA drive. The DSP and the FPGA would boot under control of the ARM core, probably when their respective Linux kernel modules are loaded.STM32 microcontrollers, especially STM32F030
two weeks ago I saw an interesting project, STM32F + Spartan6, for a portable gaming console. -
U-Boot + UEFI in the XIP NOR Flas ... SATA ... DSP ... FPGA ... ARM ... Linux kernel
it sounds too complex. I was talking about a simple gaming console, as those made in the 90s, and simpler than a SONY Playstation1, whose GTE is full of math and complex circuits, whereas the console I saw only implemented a simple sprite-engine, followed by a simple blitter, and the author said it took a couple of years of work (done during his weekends) make it "ready"
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Although having posted here a few days ago, I'm not following this thread in detail, so surely somebody has pointed this. There are modern MCUs containing some kind of external memory controllers that may be of use here. For example the STM32F767 (datasheet here: https://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/96/8b/0d/ec/16/22/43/71/DM00224583/files/DM00224583.pdf/jcr:content/translations/en.DM00224583.pdf, see section 13.5) has it. It supports a SRAM mode that mimics the traditional A+D+CS+WE+OE interface (at 8, 16 or 32 bus widths)
There are even MPU that does the same, MPU that runs stock OS like Linux. There are even interface chips that gives you similar interfaces from PCI-Express and conventional PCI bus, using an add-on card inside your PC.
Regards.
Personally I do prefer the MPU or PCIe card approaches, as they have the lowest software difficult, since the immense complexity of housekeeping is already dealt with in the stock OS. -
Although having posted here a few days ago, I'm not following this thread in detail, so surely somebody has pointed this. There are modern MCUs containing some kind of external memory controllers that may be of use here. For example the STM32F767 (datasheet here: https://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/96/8b/0d/ec/16/22/43/71/DM00224583/files/DM00224583.pdf/jcr:content/translations/en.DM00224583.pdf, see section 13.5) has it. It supports a SRAM mode that mimics the traditional A+D+CS+WE+OE interface (at 8, 16 or 32 bus widths)
Regards.
Yes they do but the memory controllers always act like masters on the bus. I have yet to see one that does the opposite where it acts as a slave to expose internal memory in the chip out to an outside master (Apart from FPGAs with ARM cores, but they have specific reasons to have that feature). -
If you want the processor to act as a bus slave, the CH368 in slave mode can be an option: it allows you access the host PC memory using regular PCI bus mastering, message-signaled interrupt and other goodies over a PCIe x1 interface.Although having posted here a few days ago, I'm not following this thread in detail, so surely somebody has pointed this. There are modern MCUs containing some kind of external memory controllers that may be of use here. For example the STM32F767 (datasheet here: https://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/96/8b/0d/ec/16/22/43/71/DM00224583/files/DM00224583.pdf/jcr:content/translations/en.DM00224583.pdf, see section 13.5) has it. It supports a SRAM mode that mimics the traditional A+D+CS+WE+OE interface (at 8, 16 or 32 bus widths)
Regards.
Yes they do but the memory controllers always act like masters on the bus. I have yet to see one that does the opposite where it acts as a slave to expose internal memory in the chip out to an outside master (Apart from FPGAs with ARM cores, but they have specific reasons to have that feature). -
Yes they do but the memory controllers always act like masters on the bus. I have yet to see one that does the opposite where it acts as a slave to expose internal memory in the chip out to an outside master (Apart from FPGAs with ARM cores, but they have specific reasons to have that feature).
Here's an interesting blog post about hacking a scope. If you go forward 10-15 pages, the author has discovered that the sampling FPGA is masquerading as DDR2 memory to connect to the CPU:
http://blog.weinigel.se/2016/05/01/sds7102-hacking.html
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Back to the roots: the OP is asking on whether somebody knows about a "modern MCU" with a traditional 8080/6800-like bus. The OP wants to drive various vintage 8bit-era 5V parts out of such a modern MCU..
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Back to the roots: the OP is asking on whether somebody knows about a "modern MCU" with a traditional 8080/6800-like bus. The OP wants to drive various vintage 8bit-era 5V parts out of such a modern MCU..
You're a show-stopper. The thread got so close to recommending Zynq
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FPGA suggestions are already flying, so I am already waiting for Zynq to show up somewhere. Although I am still standing my my suggestion: PIC32MZ DA, CH367 and CH368. All of which provides that kind of bus and runs some modern operating system (PIC32MZ DA) or inerfaces modern PC using a simple logic interface on the other end (CH367/CH368, which exposes an ISA interface or something similar to a VLB bus over PCIe.)Back to the roots: the OP is asking on whether somebody knows about a "modern MCU" with a traditional 8080/6800-like bus. The OP wants to drive various vintage 8bit-era 5V parts out of such a modern MCU..
You're a show-stopper. The thread got so close to recommending Zynq -
Just a heads up, indeed the original intention was (and still is) as @imo have said to drive a 5V 6800 (with a Z80 as bonus) compatible bus via some kind of ICE, that emulates totally something else
and can be connected to some powerful modern <fruit>Pi boar or similar via reasonable fast interface la (Q)SPI running 20-50MHz clock.
But this thread took some kind of life of its own (and I'm very happy about it
) and somehow become a nice information resource about digital design, it even convinced me (to once again) try to look into the FPGA design and I've even started to have a bit of progress. I don't know where will this will led me, I have selected on the page two of this thread some nice STM boards that have this paralel memory interface, that I will use them eventually when I give up the FPGA design 
, probably by the time I'll figh with the clocks and clock domain crossing.
Anyway, if someone is capable to design this stuff as described (for 6800 first) on a CHEAP board, like this mentioned Mojo I will still have my gratitue and some barely limited number of beers and German sausages, and they are really good
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But thanks to everybody for the contributions and keep the ideas flowing.
Cheers,
DC1MC -
... it even convinced me (to once again) try to look into the FPGA design and I've even started to have a bit of progress.
If not for the task in the original post, FPGAs are still worth exploring. Looks like you have already dealt with MCUs, and you know, they're all roughly the same. FPGAs will give you something different ... and much more powerful. -
FPGAs will give you something different ... and much more powerful.
usually, people who say that kind of things with too abnormal enthusiasm are of the same level of those claim they can do a different thing like building their own Gundam in the garage
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CH367 and CH368
This is interesting, at least for the PCI. Do you happen to have an Application Note, or do you happen by any chance to have already seen a development kit, like a PCI-Card (not ePCI, PCI! or PCI64) with that chip?
p.s.
speaking about Linux, Alan Cox wrote me an email warning that when a device is PCI-bus-master ... your life is full of troubles, in fact, a couple of drivers for our PCI_SATA controllers are not yet working as they should, not even close to the baseline, sometimes they cause the kernel to crash, and ... fixing it out is not a piece of cake. -
if someone is capable to design this stuff as described (for 6800 first) on a CHEAP board
Two years ago, I designed a 68HC11 board; hc11 is similar to 6800, with a builtin UART, timers, and ADC. Not so expensive, and not complex; the board is loaded with a monitor that works on the serial line with a human interface. On the internet, you can find even simpler boards, some use an NVRAM instead of a UV-ROM, that simplifies the circuit. I am working on a BASIC interpreter integrated with the monitor. I can give you a copy of NOICE-11, that is a way you can download and debug stuff. The other way is BUG11. Both require Windows. Here I am using Windows XP.
I have also a prototypal 6809 board, not tested yet. The firmware is very limited, sort of monitor to upload SREC files, other features (like registers dump) are not fully working, and probably the whole core's still bugged. This project is frozen at the moment since I am on 68332EVS(1), where the thing you can appreciate about CPLD and FPGA is the possibility to develop a BDM-to-gdb bridge, where all the timing stuff is done by an HDL circuit
(1) Motorola 68332, sort of 68000 with built-in peripherals; the name "EVS" is for an old development board, which offers a built-in BDM hw-debugger able to talk on the RS232 line, hence I also have a way to fully reverse the protocol. It takes a lot of time, anyway, a lot of weekends ... -
This is interesting, at least for the PCI. Do you happen to have an Application Note, or do you happen by any chance to have already seen a development kit, like a PCI-Card (not ePCI, PCI! or PCI64) with that chip?
I have the datasheet and application notes, but they are all in Chinese. Those chips speak PCI Express to the host system. If you want conventional PCI there is a different chip for that.speaking about Linux, Alan Cox wrote me an email warning that when a device is PCI-bus-master ... your life is full of troubles, in fact, a couple of drivers for our PCI_SATA controllers are not yet working as they should, not even close to the baseline, sometimes they cause the kernel to crash, and ... fixing it out is not a piece of cake.
CH367 is not capable of bus mastering. CH368 can, but it is only available in VLB bus slave mode which requires another microcontroller acting as the bus master. -
There are also PCI bridge chip used for FPGA interfacing, so that the FPGA designs need only interface to a simple 32bit synchronous local bus. The bridge chip is usually labeled "PLX" (e.g. PLX 9030, 9054) on the top and supports Bus master and DMA transfers to and from system RAM for maximum performance.
Developed in USA, with English documentation, and used by Mesa at least in a couple of boards used in our radio-telescope.
Potentially it's good, practically it requires a lot of time before it really works. -
There are also PCI bridge chip used for FPGA interfacing, so that the FPGA designs need only interface to a simple 32bit synchronous local bus. The bridge chip is usually labeled "PLX" (e.g. PLX 9030, 9054) on the top and supports Bus master and DMA transfers to and from system RAM for maximum performance.
That is why I suggest the CH367/CH368. It gives you a ISA-like or VLB-like interface in master mode (actually they intended that this chip can be used to modify existing ISA/VLB cards using as little effort as possible,) and for CH368 it also has a slave mode that is effectively a PCIe slave to EBI slave bridge allowing interfacing other microcontrollers that has a 32-bit EBI to a PC.
Developed in USA, with English documentation, and used by Mesa at least in a couple of boards used in our radio-telescope.
Potentially it's good, practically it requires a lot of time before it really works. -
Potentially it's good, practically it requires a lot of time before it really works.
That is why I suggest the CH367/CH368
that's very interesting for our next-generation of radio telescopes cards!
(yes, we are analyzing radio signals coming to Earth planet from the deep space)
can you upload some AN, or example of these CH36x chip onto the DownTheBunker's uploader?