STM32L5-series microcontrollers are sampling now and scheduled to begin production in Q2 2019.
"Out" may be stretching it a bit.
They are also not as low power as L4.. They are saying 60uA/MHz vs 36uA/MHz for L4
They are also not as low power as L4.. They are saying 60uA/MHz vs 36uA/MHz for L4
If we compare current w/o the switcher ("LDO current"),
STM32L4R5 (up to 120 MHz) 110 uA/MHz
STM32L4 (up to 80 MHz) 100 uA/MHz
STM32L5 (up to 110 MHz?) 96 uA/MHz
I notice they give the "with SMPS" number using a 3V supply for STM32L5 whereas for the older chips it was specified at 3.3V. No idea why they would change that. In any case, I think it's a wash. I don't see that the new core is going to do anything for me; I'd be more interested in the new or updated peripheral set, but I'm guessing it's pretty much the same too.
I need to know more details. I have a few samples of ATSAML11 that implements Cortex-M23 + TrustZone and has created a dev kit for it (SushiBits Micro M23 Pro) but there is little time for me to actually play around with it.
Yeah, guess you'll have to wait for about a year.
The following says more about practical use "low-powerness" than raw current figures: "achieving 402 ULPMark-CP in the EEMBC[1] ULPBench, "
It appears to be *very significantly* better than the L4 series. This benchmark has always proved useful to me in real-life applications.
"Production" time isn't that important as you can play with the samples prior.
Not clear if the USB is anything beyond USB FS with USB-3 power support. No mention of ULPI, and I assume there's no integrated HS/SS PHY - that by itself would be headline news.
Seems there's only the controller, external phy
from
https://www.st.com/resource/en/data_brief/stm32l562ze.pdf3.43 Universal serial bus (USB FS)
The devices embed a full-speed USB device peripheral compliant with the USB specification version 2.0.
The internal USB PHY supports USB FS signaling, embedded DP pull-up and battery charging detection according to Battery Charging Specification Revision 1.2.
The USB interface implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 link power management.
It has software-configurable endpoint setting with packet memory up-to 1 Kbyte and suspend/resume support.
This interface requires a precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator (HSI48) in automatic trimming mode.
The synchronization for this oscillator can be taken from the USB data stream itself (SOF signalization) which allows crystal less operation.
3.44 USB Type-C™ / USB Power Delivery controller (UCPD)
The device embeds one controller (UCPD) compliant with USB Type-C Rev. 1.2 and USB Power Delivery Rev. 3.0 specifications.
The controller uses specific I/Os supporting the USB Type-C and USB Power Delivery requirements, featuring:
• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
• “Dead battery” support
• USB Power Delivery message transmission and reception
• FRS (fast role swap) support
The digital controller handles notably:
• USB Type-C level detection with debounce, generating interrupts
• FRS detection, generating an interrupt
• Byte-level interface for USB Power Delivery payload, generating interrupts (DMA
compatible)
• USB Power Delivery timing dividers (including a clock pre-scaler)
• CRC generation/checking
• 4b5b encode/decode
• Ordered sets (with a programmable ordered set mask at receive)
• Frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the capacity to detect incoming USB Power Delivery messages and FRS signaling