u_integer/positive <= to_integer(unsigned(std_logic_vector));
the above will look like
u_integer/positive <= std_logic_vector_to_u_integer(std_logic_vector,size);
which makes less confusion and it's absolutely clear
(even if the operator's name is too long)
What happened to 'don't use std_logic_vector'?
in case, tell me alternatives
(and don't forget that ghdl has some problems with the unsigned type
when it needs to be interfaced with C-modules, don't ask me why
)
also the following doesn't work under ghdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
...
constant XLEN : integer := 32;
subtype cpuWord is std_logic_vector(XLEN -1 downto 0);
...
when alu_add =>
res <= opa + opb + (getStdLogicVectorZeroes(XLEN-1) & cin);
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
those libraries are NOT defined in ghdl and can't be used easily
therefore the "+" operator is not defined for std_logic_vector
and the attempt to simulate "opa + opb" will result an error
instead you need to use
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
along with the following ugly code
when alu_add =>
result <= std_logic_vector
(
unsigned(opa) + unsigned(opb) +
unsigned(getStdLogicVectorZeroes(XLEN-1) & cin)
);
work <= std_logic_vector
(
unsigned("0" & opa) + unsigned("0" & opb) +
unsigned(getStdLogicVectorZeroes(XLEN-1) & cin)
);
in this case "unsigned(opa) + unsigned(opb)" is allowed
because the "+" operator is defined along with unsigned
but the result needs to be std_logic_vector
both the above pieces of code come from OpenCores
therefore I assume it's a common trouble
edit:
entity ALU_arithmetic is
Port
(
enable : in std_logic;
-----------------------
opa : in cpuWord;
opb : in cpuWord;
in case, tell me alternatives
The signed and unsigned types. If a signal represents a number of index (and surprisingly many multi bit signals do) you should not use std_logic_vector. And yes, do use use ieee.numeric_std.all;
I'm a professional and use both.
For maintaining older projects originally written by someone else I use VHDL. However, for newer projects I prefer to use Verilog.
I personally prefer Verilog because I just feel more comfortable using it. It's what I was trained on in college and grad school and I feel it's a bit more readable but that's most likely just because I have more experience with it.