library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use STD.textio.all;
use ieee.std_logic_textio.all;
entity BlockRAM is
generic (
SIZE : integer := 65536;
ADDR_WIDTH : integer := 16;
COL_WIDTH : integer := 16;
NB_COL : integer := 1;
FILENAME : STRING := "LC3.hex"
);
port (
clk : in std_logic;
we : in std_logic_vector(NB_COL-1 downto 0);
addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
di : in std_logic_vector(NB_COL*COL_WIDTH-1 downto 0);
do : out std_logic_vector(NB_COL*COL_WIDTH-1 downto 0));
end BlockRAM;
architecture behavioral of BlockRAM is
type ram_type is array (SIZE-1 downto 0) of std_logic_vector (NB_COL*COL_WIDTH-1 downto 0);
impure function ocram_ReadMemFile(FileName : STRING) return ram_type is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : std_logic_vector(15 downto 0);
variable Result : ram_type;
begin
for i in 0 to 65535 loop
exit when endfile(FileHandle);
readLine(FileHandle, CurrentLine);
hread(CurrentLine, TempWord);
Result(i) := TempWord;
end loop;
return Result;
end function;
signal RAM : ram_type := ocram_ReadMemFile(FILENAME);
begin
process (clk)
begin
if rising_edge(clk) then
do <= RAM(conv_integer(addr));
if we(0) = '1' then
RAM(conv_integer(addr)) <= di;
end if;
end if;
end process;
end behavioral;
Thanks a lot everyone, i have completely ignored that something like that is not synthesizable.
What i was trying to do with it is feed my circuit a series of input from a txt and then write the outputs to another txt, creating a testbench of some short.
So if i have understood correctly, you all said that i have to create a ROM containing the whole input txt folder and then start reading this ROM to get my inputs.
Will the writing be synthesizable?
Also, the reason i am doing this is to make a post-implementation simulation, you think that it is necessary or the simple simulation will be enough to guarantee that i will get the same results on an FPGA ?
Thanks again