Hi all,
I recently got a PIC18F57Q43 evaluation board, and started checking out the MCU's peripherals. Never worked with an NCO before, and from reading about it, I can't figure out in what scenarios it would be more useful than a regular modern timer. There are some usage examples around the web, but those I've seen so far kind of turn a blind eye to the critical point.
The NCO introduces jitter in the output frequency; and between the jitter events, the output frequency is not exactly the one we want (otherwise the jitter would not be necessary in the first place). So in what kind of application is it still useful? I can see where an 8-bit timer with a significant prescaler will struggle in terms of resolution, but we have 16-bit timers now, which is not so far from the NCO's 20 bits.
Of course there are some increment values where the output frequency is accurate and jitter-free; I found 1023 of those for a 16MHz source clock. So yes, if I happen to require a 156.250KHz square wave the NCO is
exactly what I need...
but as a general solution? What am I missing? Apart from being a bit easier to set up, can anyone give me a real-world example where the NCO is superior?
Thanks,
Timer will create interrupts, interrupt latency varies, depending what the MCU is doing. Maybe you dont want to have your timer as the highest priority interrupt.
Its the same question, like asking why have an UART port, if you can just bit-bang everything.
Timer will create interrupts, interrupt latency varies, depending what the MCU is doing. Maybe you dont want to have your timer as the highest priority interrupt.
Its the same question, like asking why have an UART port, if you can just bit-bang everything.
Ok, I think I might have mixed up the PIC timers with AVR timers that can have direct access to GPIO pins.
Still, within a modern PIC, the timer output can be connected to a CLC or a CCP and from there to an output pin, "core independent". And, on the other side of the coin, the NCO has an interrupt too should you wish to use it...
Try to create an exact 3MHz clock from a 16MHz crystal, using a timer. Thats what the NCO is for ("0.0001% step size of source clock input frequency" it says at https://www.microchip.com/design-centers/8-bit/peripherals/core-independent/numerically-controlled-oscillator).
It must be a happy coincidence for Microchip then, that 3MHz just happens to be one of the 1023 jitter-free options I mentioned earlier 
(So is every other multiple of 15625 up to 16MHz, by the way)
But what if I need some other frequency?
then you can get that on average over time almost exactly. Another case would be a software PLL
NCO is easier to program. It has linear response. Higher values, higher frequency in linear steps.
Timer is not linear. It has 1/x response, more accurate at lower frequencies and less accurate at higher frequencies.
If you want to make a precise frequency sweep, NCO is the solution.
then you can get that on average over time almost exactly
Yes, and that's my question - in what real-world scenarios will I need a correct average over time, and not care about jitter?
Regarding PLLs, I don't "see it" yet - with the inaccuracies and jitter, can we really guarantee a locked phase?
NCO is easier to program. It has linear response. Higher values, higher frequency in linear steps.
Timer is not linear. It has 1/x response, more accurate at lower frequencies and less accurate at higher frequencies.
If you want to make a precise frequency sweep, NCO is the solution.
Easier to program - definitely, but that's a design decision - they could just as well put a 32-bit timer with minimal options, like a TMR0 on steroids, and it'll be simpler.
And again, it's more linear and accurate if you average over a long time, but you can't guarantee the duration of any particular cycle (in fact, in most cases you can be sure it will *not* be the exact duration you wanted)...
Little jitter is the price to pay for obtaining exact frequencies impossible to obtain with Timers.
In the frequency domain the signal is very pure.
Little jitter is the price to pay for obtaining exact frequencies impossible to obtain with Timers.
In the frequency domain the signal is very pure.
But... isn't the NCO jitter there precisely
because the output frequency is inaccurate? If I understand correctly, the small error in each and every cycle is accumulated until there's enough for a "leap cycle", kind of like a February 29th except in the other direction
[Edit: No, that's actually the same direction as in a leap year, isn't it?]
Little jitter is the price to pay for obtaining exact frequencies impossible to obtain with Timers.
In the frequency domain the signal is very pure.
But... isn't the NCO jitter there precisely because the output frequency is inaccurate? If I understand correctly, the small error in each and every cycle is accumulated until there's enough for a "leap cycle", kind of like a February 29th except in the other direction
the frequency is accurate over time. Like with leap years, the "jitter" on the number of days in a year means over time there is exactly one calender year per actual year
before the pope came up with the calender with leap days, the calender slowly drifted and a summer month would slowly become a winter month
the frequency is accurate over time. Like with leap years, the "jitter" on the number of days in a year means over time there is exactly one calender year per actual year
before the pope came up with the calender with leap days, the calender slowly drifted and a summer month would slowly become a winter month
Exactly. So what would be an embedded-world equivalent application?
Other application generating sine wave signals:
http://ww1.microchip.com/downloads/cn/appnotes/cn561389.pdf
That, I still don't understand. They add 0x84 (132 dec) to the accumulator each time, according to the fNCO formula that's 2014.16, divide by 2 it's 1007.08Hz, so how did they get such a clean 1.00000000KHz signal? Did they tweak the internal oscillator when no one was looking?
Other application generating sine wave signals:
http://ww1.microchip.com/downloads/cn/appnotes/cn561389.pdf
That, I still don't understand. They add 0x84 (132 dec) to the accumulator each time, according to the fNCO formula that's 2014.16, divide by 2 it's 1007.08Hz, so how did they get such a clean 1.00000000KHz signal? Did they tweak the internal oscillator when no one was looking?
possibly,
wonder why they used 132 (1007.08Hz) instead of 131 (999.45Hz)
... it's 1007.08Hz, so how did they get such a clean 1.00000000KHz signal?
I suspect they did not get
a clean 1.00000000KHz signal, that's merely a marker location.
There are no frequency counter readings given.
I suspect they did not get a clean 1.00000000KHz signal, that's merely a marker location.
There are no frequency counter readings given.
You're right. The perfect 1KHz frequency is just implied all over the place
Arbitrary frequency square-wave synthesis is a difficult problem. The topic comes up here every once in a while and there are always several correspondents who say things like "just use an NCO" without realizing the limitations. The Microchip NCO sounds interesting; it would be fun to see a better description of how it works. Presumably there is a PLL involved?
Otherwise, for square-wave synthesis with anything approaching "reasonable" levels of jitter you have basically two options: (1) analog, e.g. a sine-wave DDS followed by a comparator, or (2) digital black magic, like continuously calibrated delay lines, the sort of thing the experts over at the Xilinx forums tell you not to attempt in an FPGA.
Arbitrary frequency square-wave synthesis is a difficult problem. The topic comes up here every once in a while and there are always several correspondents who say things like "just use an NCO" without realizing the limitations. The Microchip NCO sounds interesting; it would be fun to see a better description of how it works. Presumably there is a PLL involved?
The link in #14 has a diagram, It has no PLL just a 20b adder from sysclk.
So it has jitter no better than 1/sysclk - for many uses, that is going to be 'good enough'.
Otherwise, for square-wave synthesis with anything approaching "reasonable" levels of jitter you have basically two options: (1) analog, e.g. a sine-wave DDS followed by a comparator, or (2) digital black magic, like continuously calibrated delay lines, the sort of thing the experts over at the Xilinx forums tell you not to attempt in an FPGA.
Yes, and even (1) needs a filter after the Sine DAC, to remove the DAC steps, to give a better sine into the comparator.
These days, there are silicon synth devices that can give reasonable results.
Here is a table I did of Silabs Oscillators, useful when on-mcu NCO is not good enough.
Notice the general price/spec trend - the higher the VCO, the better the jitter, but at the cost of Icc and price.
~~~~~~~~~~~~~~~~ SiLabs i2c Oscillators ~~~~~~~~~~~~~~~~~~~~
Device SpeedGrade Xtal Out(MHz.CMOS) MinFvco(GHz) MaxFvco(GHz) Icc Jitter
Si564.A 152.6 0.2~3000 10.8 13.122222222 87mA CMOS 95fs RMS Product Revision (B)
Si549.A 152.6 0.2~1500 10.8 12.511886114 87mA CMOS 95fs RMS
Si549.B 152.6 0.2~800 10.8 12.206718160 87mA CMOS 95fs RMS
Si549.C 152.6 0.2~325 10.8 12.206718160 87mA CMOS 95fs RMS $25/1+ ( >$8.36/10k )
Si544.A 55.05 0.2~1500 10.8 12.550082103 74mA CMOS 150fs RMS Si544: 1: $20.38 @ Mouser, 5 part codes.
Si544.B 55.05 0.2~800 10.8 12.109728345 74mA CMOS 150fs RMS ( >$6.69/10k )
Si544.C 55.05 0.2~325 10.8 12.109728345 74mA CMOS 150fs RMS
Si570 114.28 10~160M 4.850 5.670 90mA CMOS 0.62pstyp >$12/1 ONLY in 5x7 package
Si599 39.17 10~810 4.85 5.67 90mA CMOS 0.7ps CML; CMOS; LVDS; LVPECL 3.2x5; 5x7 Single $5.2884
Si514 31.98MHz 0.1~250M 2.080 2.500 21mA CMOS 0.8ps DK : $7.53/1 (10MHz.3v3 & 24M.1v8) >$2.71/10k ($5.27/1k+) 5x7, 5x3.2, 2.5x3.2 sizes (Max 2.5G/10)
Si5351A.QFN20 25~27 0.002~200 0.6 0.9 22mA CMOS ~40ps pp ~$1.82c/1k SI5351A-B-GM (QFN20 has lower jitter spec)
Si5351A.MSOP10 25~27 0.002~200 0.6 0.9 22mA CMOS ~70ps pp ~85c/1k MSOP10
Good table.
Is what I was looking for to test a frequency counter:
Device SpeedGrade Xtal Out(MHz.CMOS) MinFvco(GHz) MaxFvco(GHz) Icc Jitter
Si564.A 152.6 0.2~3000 10.8 13.122222222 87mA CMOS 95fs RMS Product Revision (B)
Si549.A 152.6 0.2~1500 10.8 12.511886114 87mA CMOS 95fs RMS
Si549.B 152.6 0.2~800 10.8 12.206718160 87mA CMOS 95fs RMS
Si544.A 55.05 0.2~1500 10.8 12.550082103 74mA CMOS 150fs RMS Si544: 1: $20.38 @ Mouser, 5 part codes.
Si544.B 55.05 0.2~800 10.8 12.109728345 74mA CMOS 150fs RMS ( >$6.69/10k )
I used the NCO as a analog driven clock source to a switched capacitor filter as part of an analog synth module. Easy to program and linear response to register settings.
I've used NCOs for lots of telecom designs. The jitter P-P (time) amplitude depends on the NCO clock frequency and the jitter spectral content (phase modulation) depends on the division ratios. While you can use the full output word and feed it into a D/A converter and filter, you can often take the MSbit output and run it through a simple L/C filter, or sometimes a SAW filter, or occasionally an inexpensive PLL, and reduce the jitter to extremely low levels. There are many types of NCOs, including arbitrary fraction types.
In my telecom applications, I often needed to synchronize multiple clocks, with mechanisms for carrying asynchronous data on a synchronous channel, and sometimes regenerating the asynchronous clock at the other end. Legacy telecom networks seem to like using prime number-related clocks, so simple dividers just won't do the job. NCOs and their relatives can provide the required precision, stability and flexibility, and can do it at a much lower cost and smaller footprint than the traditional VCXO PLL designs.
While you can use the full output word and feed it into a D/A converter and filter, you can often take the MSbit output and run it through a simple L/C filter
Thanks for the information, but I'm either missing something or it's not relevant to NCO modules in microcontrollers - there's no "output word", just the final output signal...?