"Just last week I fixed an eerily relevant problem where I was..."
That proves that you are a good human programmer, , because only fools would assume that his code is bug free while debugging it.
The issue at hand is very easy to debug, as the bugs are painfully obvious.
[...]
SOT23 = TO-236AB ?! ... naturally.
i don't really know why you assume i don't understand that hardware needs to be debugged and why you further assume that i have _not_ debugged the problem to the extent needed
Bob seems to be my uncle.
I am a bit surprised about your belligerent attitude because i fail to see what i did to deserve it.
Ooops, I deleted my thread too late. Impulse. Please disregard. Or should I put it back?
My intention is not to ruffle feathers.
My previous post was unfortunately not saved in my clipboard. But as you say, whatever. I'll accept belligerent, as long as the content of the post is also conveyed. Which is to say, if I don't assume anything and go by what you have written, what you have strictly written is slightly lacking in the scientific process. And the conclusion (behavior between 0 and 40mV) so very curious as to merit a more bulletproof verification, maybe. The datasheet suggests the difference there should be between that of jack and @#$#, and jack left town. (Army of Darkness!)
40mV is a perfectly acceptable CMOS digital low output. The output FETs of the CMOS micro pins have a significant RDS, themselves. (What load do you have on there that might be pulling the pin up to 43mV? Who knows? I thought it was just the FET on this pin, which is only capacitive?) Any rate, a logic level FET that changes RDS from megaohms to kiloohms between 0 and 40mV Vgs is a curiosity. At below standardized CMOS logic low, this thing acts like a 50K resistor.
Perhaps you have done a sufficient proof, already, but you did not write it. Perhaps you know you didn't do this, and you don't care. Either way that would be fine. I am posting this because you came back to declare the proof is done... it "seems," without an explanation beyond, "I swapped these crappy FETs with these good FETs and my circuit is now working as I intended. The 2n7002 is crappy. And the problem was not my code."
Extraordinary claims require extraordinary verification. I'm not the only one thinking it. I'm just the idiot with no filter. I'm ordering some resistors from Mouser, and what do you think the chances of me replicating your results are going to be if I add 2n7002 NFET to my cart?
Besides that, I just googled CMOS output voltage levels, and I had to correct my previous post. The max is apparently defined at 50mV, which is a surprise to me and puts a new twist on this. At first, I didn't think anything of 43mV. 43mV is small. But compared to 50mV max, it is a lot.
If his output pin is low, and it's only connected to a FET gate, then should it even measure 43mV? CMOS output is through a FET, itself, which is a purely resistive voltage drop. And with no load, would it even be that high? Where is this 43mV of drop coming from?
So if an output pin is rated for 25mA, let's say, it has to be able to sink 25mA and still maintain 0.05V, max. At a microamp (to cover gate leakage, lol), it should be much less. At 43mV, if the Atmega actually meets spec, this suggests the pin is sinking at least (if not more than) 4/5th of its max output rating simply holding a signal FET gate down. (Or that his pin maybe isn't doing exactly what he thinks it is. Which sounds more plausible?)
So I have a PIC project already wired up on my bench. And I just measured voltage on a PIC output pin digital low with no load. Supply voltage 5V. Pin measures 0.000V. Nada. (And of course I also verified it gives ~5V when the pin goes high to validate my test setup!)
For giggles, if that 43mV were coming from an intermittent high output or an internal pullup resistor, 0.043V/5V is a duty cycle of 0.86% at 5V (or 1.3% at 3.3V), if I'm not mistaken. Enough to give an LED a decent glow. Due to the capacitance of the gate and the rise/fall times of the pin output FETs, the actual duty cycle of the pin might be considerably smaller than 1%, if the frequency is high. This is a situation that might occur... if the ISR is using that pin, for instance. A UART ISR, for example. Just one possibility to consider.
The GPIO pins have more electronics than just a simple fet totem pole connected to them.
Atmel data sheet specifies DC electrical characteristics as Vol@5Vcc as 0.9V max
Some of these things you can test in less than 60 seconds. You could squash my theory in no time. Yet you continue to pontificate. Perhaps you already did some of these things? Or perhaps you have shrugged off some quirk you have already noticed which is suggestive. Perhaps you still hold out hope that there is an alternate explanation where I am wrong? Do you hate me this much?
For giggles, if that 43mV were coming from an intermittent high output
You could squash my theory in no time.
A plausible explanation
this is not a DC problem.
0.1ua at 1.34v Vgs.
To think a FET turns on at 40mV is similar to believing a red LED will glow at 100mV.
I am not sure how you are measuring this.