My design preference is to use net labels instead of wires to connect signal bunches.
My design preference is to use net labels instead of wires to connect signal bunches.Hmmm! Let's see if I have this right. You are providing a file in a format (7z) that would require me to jump through several hoops in order to undo it on a Linux platform. Then, if I jump through those hoops, the schematic is essentially unreadable to anybody who doesn't already have the insider-knowledge of its creator.
The only benefit you will get from this format and a "peoper ee101" style is you can see there are 2 spi buses, a 8bit data bus and 3 differential serial io pairs.
Er, it's just a 7z, there's not a lot of hoop jumping there.
Er, it's just a 7z, there's not a lot of hoop jumping there.It is not a format that I can readily open. The limited research that I have put into opening these files is suggesting that I will have to cobbled-together some software to undo a format that is centred on M$ technology. May it's not much of a hoop if you already have that unzipper, but it is further than I am prepared to jump.
The "fuel gauge" I mentioned is a Li-ion fuel gauge. Because this design requires quite some power, and I want to make it portable (smart phone accessory), I need to get power to it without draining cell phone batteries too fast. Therefore I decided to make an battery enclosure for it to power it. I need to let the device know how much power is left in the battery, so I took leverage of the unused ID pin as a low bandwidth single direction uart pin.
For the performance part, I sincerely know that human ear is the golden standard, not test equipment. The reason I care about test result is because I can introduce distortion and flavors in DSP, but I can not do too much to reduce them. Therefore, the system hardware should be as ideal as possible, so I have more space to tweaking the DSP algorithm to make it sounds better as per human ear perceives.
In the OSHW world there are no secrets. Maybe I will get profit by providing "device cloning" service, so that I can create customized "profiles" for any samples the customer provides. Or I can make money by sublicensing companies to do non-open source derived works.
DSP code will be USB stack, cubic, polyphase FIR and FFT filters that the industry used for tens of years. There will be some black magic in reducing calculating complexity, but anyway I will publish it somewhere such as IEEE some time, so there are really no magic.
For the real interesting part, how to eliminate non-linear distortion, I referred something from ES9018's patent, but took a huge detour, so it won't violate any patents. These parts (SDM, DEM and calibration) are done in FPGA. All FPGA diagrams, HDL code and test benches will be open source.
There are nothing too excited in the ASIC, and if you want, you can build it with a FPGA and a shitload of logic gates and resistors with a couple of transistors. The only reason I decided not to open source the ASIC design is because the process provider doesn't allow me to do this.
The final product is WAY smaller than HUGO. The finished assembly is estimated to be smaller than 25mm*60mm*8mm.
Can I say all the circuits you described, power, fpga,dsp, usb and dac are on this one single pcb? What about the connectors, power, usb,signal output like RCAs, etc? What is more surprising to me is what caps
are you using for signal analog coupling? All I see are smt footprints and no throughhole components.
Analog part will be on a daughter card. For the caps, mlcc will be used. Don't be surprised, with careful design mlcc can be used. Of course, only np0 will be used in signal path, and they will only work as very frequency lpf. Otherwise it makes no sense to take so much effort to do 128-256x oversampling. Connectors will be only micro usb and two 3.5mm jacks.
The dac will be an asic. I got a deal from csmc and they can offer me 0.5um 2p3m mixed signal process for $2500.
For the caps, the dac board has enough space to let me implement film caps based filter, so if needed I can squeeze some space from other modules.
Is your asic dac same as Hugo's 32 bit? Want to be sure we compare apples with apples, looking forward
to your giant killer.
4 bit thermometer dac. Sigma delta modulation is done on fpga.
External iv, but with current mirror, so slower speed of opamp won't create trouble. Also, there are measures to tackle down inter symbol interference.