I'm looking at the AD629 Difference Amplifier.
http://www.analog.com/static/imported-files/data_sheets/AD629.pdfIt has a +/-270V common-mode voltage range, and input protection to +/-500V common mode. That all sounds great, but how do they do that in an SOIC-8 package? The pad-pad spacing for SOIC is around 25mil. Aren't the pins way too close together for that big of a voltage?
Assuming a +/-15V split supply referenced to the system ground with the ref pins grounded (like the basic connections figure 32 in the data sheet), wouldn't pins 1 and 4 be way too close to the differential input at pins 2 and 3 for a 270V potential? What am I missing here? Did I just break the first rule of high common-mode voltage difference amplifier club?
Conformal coating after cleaning during assembly. Input protection resistors, creepage distances and voltage overload protection for mains work will also be needed. In mains work I would use the DIP version anyway.
If your PCB manufacturer offers such possibility, then routing out the laminate between IC legs and pouring good insulator there (some kind of silicone?)
Conformal coating is way too much of a production hassle and just adds cost. I'm just amazed that if conformal coating is REQUIRED, that it's not mentioned anywhere in the data sheet or any of the app notes. Even with the DIP package, the pad-pad spacing is still only around 40mil, which for an outer layer isn't enough for 270V unless you are in a clean room, which it not the case here. From what I understand you are supposed to have even more clearance anyway for things like through hole pins sticking out of the board.
I found a topic in the AnalogDevices Engineering Zone forums, but it doesn't look like anyone form AD actually responded. I bumped it.
http://ez.analog.com/message/49711#49711
In case anyone was interested, the other high common-mode voltage diff amps I found are:
TI = INA149
and while not exactly the same, but pretty close
Linear Tech = LT1990
ever wondered how a diode's depletion layer can hold 1000 volt like in an 1n4007 ... knowing that layer is microns thick ?
it will hold pin to pin.. if it won;t creep over the surface of your pcb is another story , especially when that pcb starts collecting dust and grime ...
For the most part, that surface contamination conduction is what you are addressing with conformal coating. It's also why there are complex tables that need to be deciphered to figure out what the minimum creepage distance is for a particular PCB for a particular application based on the contamination level. The inner layers of a PCB are effectively shielded from contamination which is one of the reasons clearance requirements are less on inner layers.
Arc over distance is all about whatever the dialectic of the material is. Open air conduction at room temperature and sea level isn't really the issue. The dialectic for air ends up with about 3MegaVolts/meter, or 2-3kV/mm. That's saying for 275V, you only need an air gap clearance of around 0.1mm(4mil) to keep it from arcing. Now if you used that as a clearance for a PCB on a board with the AD629, don't expect to get through any certification process, and you better be running in a clean room.
I'm totally cool with the AD629 requiring conformal coating to reach it's specd voltage rating, but they really should say that in the data sheet.
Cool! The AD guys actually responded to that post I made on their forum. Here is what he said:
Hi VT,
You are correct in that the pin spacing presents issues at high voltages. The AD629 comes in a 8-Lead SOIC and an 8-Lead PDIP. The two packages have lead spacing (middle to middle aka lead pitch) of 1.27mm and 2.54mm respectively. The packages also have lead widths of 0.41mm and 1.52mm (typical values). These two factors give a minimum clearances of 0.86mm and 1.02 mm between high voltage input leads and the reference (usually ground) and the -Vs (typically -15V.
Mapping these spacing values to maximum voltage levels is fairly straight forward in that you just need to determine what specs you are trying to conform to, for example IPC-2221, table 6-1, (unfortunately I can't directly quote this spec here). For this spec, the 0.86 spacing would gets you to 150V under some conditions and 500+ on others (coatings being one of the differentiators).
In my opinion, it would be out of the scope of a typical amplifier datasheet to determine which PCB spec a customer is likely required to meet and what their options are for meeting any given spec, but it is a fair point that it ought to be mentioned in the datasheet that this could be an issue.
Regards,
Paul
Interesting. So a quick Google search for IPC-2221 and the first result was:
http://classes.soe.ucsc.edu/cmpe174/Fall12/References/AppNotes/IPC-2221.pdfI wonder if they will actually update their datasheet. I don't think I'm going to hold my breath, but good job AD for responding.