... There was a guy here who tried to do a 10 Ghz sampling scope. He had a working prototype yet he didn't manage to get the necessary funding on Kickstarter.
Any suggestions for a low jitter, picosecond scale delay timing chip?
One that can go up to 5.8GHz or so would be very useful for analyzing 802.11.
In general the approach of using a startable ring oscillator has the disadvantage, that for fast start up, the oscillator should have low Q, but for low jitter it should have high Q.
Some years ago, I've been into building a sampling scope using the comparator-as-sampler approach. Unfortunately, I never finished it
Sampler comparator was an ADCMP582.
For trigger generation, I used a startable ring oscillator (basically an and gate and transmission lines on the PCB) and an MC100EP196 delay line with analog fine tuning. The ring oscillator's output is divided by 2 to to reduce the length of the delay line. This signal is fed an ECL counter, that generates a pulse every 256(?) clock cycles. By presetting this counter, I can control the sampling instant with a granularity of approx. 10ns. To get down to ~1ps, the delay line is used.
Since both of these delay elements are rather inaccurate, the MCU measures the frequency of the ring oscillator. To calibrate the MC100EP196, it can be configured as ring oscillator as well, so the MCU can measure its frequency as well.
Unfortunately, I haven't been to characterize the start-up behaviour of the ring oscillator yet.
In general the approach of using a startable ring oscillator has the disadvantage, that for fast start up, the oscillator should have low Q, but for low jitter it should have high Q.
Anyone got any expericene with going the analog way? I.e. steering currents in and out of a capacitor for ramp generation
In general the approach of using a startable ring oscillator has the disadvantage, that for fast start up, the oscillator should have low Q, but for low jitter it should have high Q.
Why would that matter? You aren't relying on noise to start the oscillation are you? You said AND but I assume you meant NAND, the trigger makes one input high, output goes low and cycle starts ... how does high Q matter?
The problem is that your first cycle starts with a gate signal shape different from the steady state, so it will take a while to settle. A high Q simply means insensitivity to such effects, but it would still instantly start up. The higher the Q the better.
random, non sync'd triggering? Then using known sequential time slices to sample the waveform for up to 10nS? But the EP196 isn't giving a reliable, known, delay and needs calibration?
The Ep196 appears to have a 16.7 pS timing drift per °C rise. That is a lot for the app. Looks like you might need to do a 0.1°C accurate Oven controlled box for it.
Then it has > 120ps Tr so how accurate is this going to be for the app?
IIRC, I read that fact about Q factor in some paper about sampling scope timebases and considered ist plausible. Maybe I can find that paper again.
I'd love to have a 1 to 1.5 Ghz sampling head. Especially if it were a dual head for comparative phase measurements.
One of my friends has an ancient TEK 1 Ghz sampler and it has turned out to be quite useful...
My contribution to the initial research reading is attached, it makes a nice test pulse. It was designed by Dr. Houtman who did the delay line sampling scope plans mentioned earlier. When one does a little digging into Dr. Houtman's academic work, its very clear he knows his way around very fast phenomena.
I love the colliding wave architecture he used to make a symmetrical pulse..
Steve
Perhaps I should indicate that since this is targeted for folks who can afford modern 100Mhz - 200Mhz scopes etc, perhaps in the $400 to $1K range, the DSO/PC compatible sampling head should also be limited to that range.
While using vintage tek/HP equipment and CRT photography to do the job is fun, something a bit more PC and DSO friendly is warranted for modern signal analysis convenience.