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Horrible waveforms on rectifier bridge output in a motor driver :|
Posted by krisRaba on 13 Apr, 2021 09:46 -
Hello,
I have a question about waveforms on rectifier bridge output.
In a motor controller (HV) I have an AC input stage like on schematic attached below (pic 1). I have noticed that when motor is enabled nearby placed I2C bus (usually quite sensitive to any noise) crashes so I started my investigation
All "academic" waveforms that I remember looked mostly like these on picture 2 (when motor is disabled) - my reference point is PE (because I don't have differential probe), DCBUS+ (yellow) fluctuates above PE level and hot GND (blue) fluctuates below PE. Nothing surprising so far...
Then output stage for motor is enabled. It is a triple H-bridge controlled by a motor driver IC. When it is enabled all motor outputs start switching (50% PWM). If any motor rotation is desired PWM duty is adjusted and "mismatch" between them on motor phases forces current to flow etc.
But what is a big surprise for me is the picture 3 where that switching (without any motor rotation, just motor enabled, all PWMs in phase and with the same duty cycle) affects "standard" output waveforms of rectifier bridge so much
When zoomed in you can clearily see PWM over that.
I though that DCBUS and GND levels are strongly forced by the mains network and the rectifier bridge
Of course when you subtract one waveform from another it is "ok" and you will get the DC level (on differential probe between DCBUS and GND you probably would not see any problem) but referring to PE everything looks like an EMC nightmare
Mentioned I2C bus is a first victim...
I have also checked how does it look when resistive load is connected to the output stage instead of motor windings (pic 6) and waveforms are then affected only a little bit
Do you have any idea what is going on in here? How to fix that? How to decrease the noise?
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Some PWM signal will be present there because of the capacitive coupling to Earth from the motor windings to motor frame.
The only Y capacitors shown will be doing nothing while D1 diodes are not conducting. The Y caps should be checked anyway for loss of capacitance. -
Some PWM signal will be present there because of the capacitive coupling to Earth from the motor windings to motor frame.
"Some" would be ok, I think. But PWM amplitude measured there is ca. 136V
The only Y capacitors shown will be doing nothing while D1 diodes are not conducting. The Y caps should be checked anyway for loss of capacitance.
What do you mean? Unfortunately I don't undestand that statement.
Y caps in the filter are quite new so I doubt that anything is wrong with them.
Generally speaking this motor controller works properly in terms of base functionality. The problem I have noticed is the noise that corrupts I2C transmission etc. -
The D1 diodes spend a lot of time not conducting. During this time, there is no path between the DC bus and the Y caps.
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Ok, as far I understand you mean that voltage on DCBUS is higher that AC input so D1 is reverse polarized and not conducting. Like on attached picture...
But are you suggesting some kind of improvement that could be done or simply commenting a fact?
I have seen such topology on few schematics so it doesn't look weird form me. But maybe it should?
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I think what you are seeing is normal. I can't be certain what level of PWM signal should be there.
The level of PWM signal should be less while D1 diodes are conducting during mains cycle peaks.
In other words, the PWM signal should be modulated with 100Hz. -
Still playing around and another interesting thing I have just noticed is that output PWMs amplitude is lower than expected, ca. 192Vpp. When we add 136V of amplitude noticed earlier over DCBUS and GND we get 192V+136V=328V! So something seems to be really screwed up in here
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As long as you're using PE as the reference point, everything you see is normal and quite as to be expected. Most of it caused by capacitive coupling the PWM output signal from motor cable / motor windings to PE.
You could attach (large ~ 100nF) Y caps from DC Bus - and DC Bus + to PE. This will shift the potentials, so you should see less PWM amplitude from DC Bus to PE and more from U/V/W to PE. Anyway, I'd advise not to do so as this measure has a large impact on total EMC behaviour of the system (can get better or worse). PWM frequency capacitive leakage current could also cause these caps to fail, as standard Y caps aren't designed to deal with these currents.
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As long as you're using PE as the reference point, everything you see is normal and quite as to be expected. Most of it caused by capacitive coupling the PWM output signal from motor cable / motor windings to PE.
You are right. I have checked with quickly acquired differential probe and phase U vs GND seems to have expected amplitude
Too much panic
But it is noisy anyway. Any suggestions how to improve that?