So my adventure into CPLD software has been extremely disappointing. No only are there only a few CPLD vendors (same with FPGA), there software support for their CPLD devices is very poor. It seems like most (if not all?) can only synthesize verilog 2001 or maybe 2005 (unclear with some software). I can't find any one than can synthesize SV2012. Is this only supported with modern FPGA synthesis tools?
CPLDs are typically very simple devices. What's wrong with Verilog-2001? What exactly are you missing from SV for CPLD development?
It's not just CPLDs. From what I gathered, SystemVerilog is still poorly supported by many vendors.
CPLDs are typically very simple devices. What's wrong with Verilog-2001? What exactly are you missing from SV for CPLD development?
They may be simple devices but SV2012 support is in the software layer, so I don't know why they would not support it. FSM coding is much better looking with SV2012 support with typedef enumerations, and in general there are quite a few datatypes that Verilog 2001 doesn't support.
It's not just CPLDs. From what I gathered, SystemVerilog is still poorly supported by many vendors.
That is disappointing. From what I can see, there are NO CPLD manufacturers that support SV2012 with their IDE suite. Zero.
If I move up to the expensive FPGA device they probably support with their 10k/license IDE software however
so I don't know why they would not support it.
I know exactly why. Testing and QA of the software will take more resources while adding little value. Companies cut software features all the time because if this.
CPLDs are typically very simple devices. What's wrong with Verilog-2001? What exactly are you missing from SV for CPLD development?
They may be simple devices but SV2012 support is in the software layer, so I don't know why they would not support it. FSM coding is much better looking with SV2012 support with typedef enumerations, and in general there are quite a few datatypes that Verilog 2001 doesn't support.
You should just use VHDL and you’ll get those enumerated states and more useful data types, most of which have been in the language for 25 years.
CPLDs are typically very simple devices. What's wrong with Verilog-2001? What exactly are you missing from SV for CPLD development?
They may be simple devices but SV2012 support is in the software layer, so I don't know why they would not support it. FSM coding is much better looking with SV2012 support with typedef enumerations, and in general there are quite a few datatypes that Verilog 2001 doesn't support.
You should just use VHDL and you’ll get those enumerated states and more useful data types, most of which have been in the language for 25 years.
I agree with that but I'm smelling the start of a flame war!
CPLDs are typically very simple devices. What's wrong with Verilog-2001? What exactly are you missing from SV for CPLD development?
They may be simple devices but SV2012 support is in the software layer, so I don't know why they would not support it. FSM coding is much better looking with SV2012 support with typedef enumerations, and in general there are quite a few datatypes that Verilog 2001 doesn't support.
You should just use VHDL and you’ll get those enumerated states and more useful data types, most of which have been in the language for 25 years.
I have no experience with VHDL nor do I have any intention of learning. I rather just live with Verilog 2001.
You should just use VHDL and you’ll get those enumerated states and more useful data types, most of which have been in the language for 25 years.
I have no experience with VHDL nor do I have any intention of learning. I rather just live with Verilog 2001.
There you go! Problem solved...
You should just use VHDL and you’ll get those enumerated states and more useful data types, most of which have been in the language for 25 years.
I have no experience with VHDL nor do I have any intention of learning. I rather just live with Verilog 2001.
There you go! Problem solved...
sigh, no ideal, but fine.