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L2 I added because I was struggling.
C20 22pF I selected based on antialyasing calculation to keep the low pass as 14X sample rate. Maybe this only applies to after the buffer?
Also noticed that taking Keithly from parallel from input of the circuit it reduced further 10uVpp the noise.
BR,
Jorge
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L2 I added because I was struggling.
C20 22pF I selected based on antialyasing calculation to keep the low pass as 14X sample rate. Maybe this only applies to after the buffer?
Also noticed that taking Keithly from parallel from input of the circuit it reduced futher 10uVpp the noise.
BR,
Jorge
With that coil you may easily pickup noises (unless it is a toroidal core). It may even resonate with that 680pF.
Why would you need the first low pass at 14x sampling rate?? You have one at the ADC input (as Andreas has recommended the values). Try with C20=10nF (foil or C0G) and look at the output data.
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The coil is this type in picture.
Maybe I didnt fully understood the antialiasing filter behaviour. I know the signal we care is much lower so the Opamp input probably doesnt care with frequencies at sampling rate. I will try first increasing C20, and then the coil if nothing.
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Your "ADC sample rate" is aprox 7 Samples per second (say 7Hz). I would set the first low pass to 2Hz, for example, with 1Meg the C20 could be, say 330nF.
Your coils - provided the small toroid there is the "ferrite bead at GND wire" and the L2 coil is the "green resistor like stuff" your L-filtering attempt is not good.
Take the small toroid and do pass the BOTH GND AND INPUT WIRE through it say with 2-3 turns. Get rid of the green coil. -
I think ADC is doing other stuff like averaging and other and justs puts out the data 7 times per second, or?
They mention in the datasheet sample rate of 153Khz.
Anyway antialiazing I think cames if bandwith of the signal persent at input of ADC/output of buffer is bellow 14x the sampling rate, but then I guess is this is more the speed of Opamp which needs to ensure the signal integrity for that bandwith.
Our signal of interest is just near DC. So filter until input of opamp can be lower frequency? Still trying to fit the requirements in my head.
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Read my previous post on your coils at your input (!).
The "ADC's clock frequency" (your 153 kHz) is the internal rate at which its sigma delta converter operates.
The "ADC's sampling rate" is the number of input voltage measurements (samples) per second, with your ADC max 6-8 per second (6-8Hz) people say.
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I observed the sampling events with osciloscope at output of buffer and is in the realm of 5uS, so close the 153Khz.
But I guess for the buffer input this is other story.
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Yes, those are 2 different stories. The input divider R with C20 should create the low pass at the input of the opamp for the ADC's "sampling rate" which is around 7Hz.
Clean up the stuff with the coils, make the common mode choke on that small toroid you have there (use a thin wire, see above the picture), and play with the C20 value (I would try up to 330nF).
Note: with the input divider connected (the relay ON) the input filter time constant will be aprox 1Meg*C20, with the relay OFF it will be aprox 9Meg*C20..
PS: the relay - I would definitely use a transistor for driving the relay off the ISO..
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The SD ADC is an integrating type, at least approximately. There is not need to have a classic anti aliasing filter for its data rage. There is already digital filtering as part of the SD ADC to suppress those lowr frequencies a classic AA fitler would suppress. It only needs AA filtering for the much faster (~153 kHz) rate for the input samplig as part of the ADC inner workings.
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Added the modifications didnt helped much.
220nF, super slow raising and still 59uvpp noise with average of 15 samples.
After reviewing the circuit I noticed I had set the 220nF capacitor between the reed relay terminals. Not sure as this resulted in this behaviour as should be a short anyway (100mOhms when relay closed).
I noticed when voltage raising some jumps like if opamp was consuming current at peaks. Maybe the bias current is too big or something.
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A little filtering with C20 is good, e.g. to limit the BW the amplifier sees at it's input. No need for 220 nF, more 220 pF or maybe 1 nF are reasonable compromise.
It still looks like there is something really wrong, like hum, supply ripply or something oscillating (e.g. the 18 kHz in post #132, what ever point of the circuit this is).
For a test one could try first with a hard 0 V sinal at the input and directly at the ADC input and than as a next step incluse the buffer. -
Hmm, I would not expect 40 minutes to settle..
My sim shows aprox 0.8sec to come to aprox 9.9V.
You need 22 minutes for the same..
Hmm, something is wrong.
Or Arduino code/MATH error?
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Thanks for the suggestions, will continue to troubleshoot next week as Easter breaker is coming.
Before I go just checked the analog current consumption. 16,82mA with 7uA variation. -
Hello,
I fear that there are several problems:
- The OP-Amp is not suited for a input impedance of 1 Meg. (choppers generally need below 10 .. 100K)
-> you will need either a J-FET type or a low input bias current type + some offset adjustment from time to time.
- USB power + capacitive coupling between digital + analog part.
I usually make the coupling capacities as small as possible. This includes also to put the shielding somewhat away from digital ground planes.
- I am not shure about the ISO part. (Simply do not know it).
In datasheet they have some EMI measures. Usually this works only for small bandwidth EMI receivers and makes it worse for analog cirquits.
What you should keep is R8 + C16 + C21 (I usually use 825R + 680 .. 820 pF).
This helps against the voltage spikes comming out of the LTC2400 and prevents that the buffer OP-Amp gets disturbed. (gives ~30 uV offset due to rectification on the output clamping diodes)
It has a reason why I use battery supply and photocouplers.
This helps against many (not all) noise problems.
And might be a good start to exclude your noise source(s).
with best regards
Andreas
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Indeed.
I did some simulation with AD8628 and is not so clean with this circuit. Current noise even gets worst with bigger C20.
ADA4522 I think is still the best bet.
Other issues will solve after op-amp.
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I don't think the models are that good to really tell the difference between the different Az op-amps. They can be both overly optimistic and pessimistic in such details.
I am afraid it would need real life tests for this. Even that datasheet values on the noise are not that reliable - some get worse when used as a buffer.
The ADA4522 is likely a very bad choice, as a version with rather high current noise. I have used MCP6V66 and MCP6V76 (somewhat similar to the AD8628) with 500 K source impedance with not so bad results. In my case also the a AD8628 is not so horrible with 10 Mohm.
My guess is more with a problem from the supply or the RF isolator.
A good JFET amplifier (e.g. OPA145) may be an option, but with different weak points. It could still be good enough for 5 digits, at least for not too small voltages. -
you will need either a J-FET type or a low input bias current type + some offset adjustment from time to time.
Except for very old designs from maybe as late as the early 1970s, all of the digital voltmeter designs I am familiar with enclose the high impedance buffer inside of some variety of automatic zero loop, typically with the automatic zero cycle preceding each measurement.
Where it gets tricky is that the automatic zero cycle may or may not correct for common mode rejection. If it does not, then the common mode rejection of the operational amplifier used as a buffer becomes very important. That makes parts like the OPA140/OPA141/OPA145/OPA1641 amazing.
I guess the next step up is to bootstrap the input buffer to increase common mode rejection, although I have only seen this in electrometers because they need an input buffer to cover a wide input voltage range.
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With only a 5 digit target there is no need to improve on the common mode rejection or input impedance. Another reason for bootstrapping the supply can be the limited supply range (e.g. 5.5 V max) of many AZ OP-amps. As an example this is done woth the Keithley 2000 DMM as the buffer at the input - though not bootstrapping in the strict sense from the output side, but more feed forward from the input.
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With only a 5 digit target there is no need to improve on the common mode rejection or input impedance.
I first ran across this problem with the old Siliconix 4.5 digit integrating converter chipset. Their automatic zero cycle did not correct for common mode rejection of the integrated CMOS input buffer, which could have been worse than 72dB when 86dB was needed, and I guess nobody realized in time that this would ruin the accuracy. They released an update which brought out the signals after the input multiplexer so that an external JFET precision operational amplifier could be used. Precision JFET parts were better, but could barely meet the requirements back then. They recommended the Analog Devices AD542 which was about the best available part at the time. These days there are lots of outstanding JFET parts which can handle 6 digits, and 7 digits with grading. The OPA145 series amazes me.
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Their automatic zero cycle did not correct for common mode rejection of the integrated CMOS input buffer
How can this correction be made automatically? -
Their automatic zero cycle did not correct for common mode rejection of the integrated CMOS input buffer
How can this correction be made automatically?
Common mode rejection is the change in input offset voltage for a change in voltage at the non-inverting input, so to have the automatic zero cycle remove that error, the buffer must be zeroed with the input voltage applied to the non-inverting input instead of applying zero or ground. As the input changes, changing the non-inverting input, the automatic zero cycles then follows it and corrects the common mode error as part of correcting input offset voltage.
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I am still targeting 6 or 6.5 digits. I just posted here where this specific ADC and Opamp buffer was in discussion. If target would be 5 digit I would just add digital filter on top and would be there.
My target is to monitor other references with a mux(MAX4051) and as such low impedance was not absolutely required, but I also want possibly to use it behind that, and as such high impedance is required. I have two temperature NTC rigged to the Arduino which I can log in parallel, and as such with single equipment I would be able to monitor multiple references and temperature variation with a single equipment.
I will test other AZ with this circuit. From the simulations I saw that Ad8628 is spread spectrum and current noise is all over the place, so maybe this is why I see noise. Since other AZ are constant current noise, maybe this will translate in constant offset which I can then get rid with calibration.
If this will not result will focus on the JFET with bootstrapping. Then I will need to change architecture, power supply, maybe negative and positive rail, and new boards. Maybe even LM399 as reference, but then other requirements for power supply. A lot of more work just to monitor a few references in parallel, and more cost as well.
My immediate next step when I get back home is: Reduce C20 back to 2nF or something, remove 10nF capacitor between digital and analog ground to make sure it is not bringing noise from laptop to analog side; use other AZ; test speed of PC817 for SPI as I have a bunch around, and maybe can replace isolator with a solution based on it in case noise is traveling through the capacitive isolator -
As Kleinstein points out, nothing exotic is required anymore for 5 or even 6 digits. If you find a chopper stabilized part which is suitable, then it will work without anything further. A JFET part like the OPA140 or OPA145 is good for 5 or 6 digits without any further correction except for input offset. I wish these had offset null terminals but input offset can be removed in other ways.
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The 1:10 divider at the very input may could be a weak point of the proposed circuit. Even the relatively expensive Caddock dividers have a limited stability and the high impedance naturally comes with some extra noise and makes it a bit tricky to use an AZ amplifier. For measuring voltage references at some 10 V one may want a different front end. More like a buffer at the input and only than some divider with a smaller ratio, like 1:2.5 or maybe even only 1:2. A divider at some 50-200 Kohm can be more stable than at 10 M. One would still also need some protection for the input, but this may need to be before a MUX chip.
The large 18 kHZ singal in the sope trace is definitely a problem - more like a supply problem, not so much a thing with the amplifier. Checking the supply and maybe an alternative to the ISO part can be a good idea. -
Just simulated ISO7762 and it seems that it is introducing 1VPP noise signal proportional to capacitor between Digital and Analog grounds through the reed relay coil that most likely is then capacitively coupled to resistor network in the buffer input. Simulation is with the cap I have in the circuit (10nF) and results on oscillation on the order of Khz. The larger the cap between grounds the lower the frequency the oscillation.
This isolator is based on OOK and this instability is probably the source of the noise I get.
I guess I should avoid use large capacitor. This oscillation would be limited but other CMM noise could get in from USB side.
There is noise also on the other signals "High" but more evident on the coil "High" value.
If I simulate PC817 then it gets limited speed of around 2Khz. What optoisolator people are using and with which SPI clock?
Or maybe I should just remove the cap between grounds and add low pass filter on the digital signals distributed in the analog board and drive the reed relay with low pass filter and Emitter follower?