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That's what I get for looking at the data sheet on my phone - no context. The register addresses are in octal
I think all of the data sheets are scans but the link C posted a while back is better quality. -
That's what I get for looking at the data sheet on my phone - no context. The register addresses are in octal
I think all of the data sheets are scans but the link C posted a while back is better quality.
Ah yes, that was it. Just noticed the jump from R7 to R10 in the docs myself. Who in binary hell uses octal?
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Who in binary hell uses octal?
YOU if you really want to understand the Z80!!!!
There are 8 RST instructions
There are 8 Condition codes
There are 8 8-bit registers. Note that here 110b is special
Look at the Specification sheet, 3 bit fields all over the place.
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Who in binary hell uses octal?
YOU if you really want to understand the Z80!!!!
There are 8 RST instructions
There are 8 Condition codes
There are 8 8-bit registers. Note that here 110b is special
Look at the Specification sheet, 3 bit fields all over the place.
Thanks for the M. Night Shyamalan moment, C!
I'm still no closer to getting output working though. Will have to take a break for a few days.
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Find a numerical order list of Z80 instructions and add a octal field for instruction values.
in octal FFh is 377
Their is 4 8x8 arrays of instructions.
16-bit instructions are in the above with 2-bit fields
Some instructions like CB & ED are toggles to expanded instructions.
Blanks in what Zilog lists for these tables are often working with IX or IY in place of DE or HL
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For each of the registers, can you read back the data that was written, do you get the value you expect?
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For each of the registers, can you read back the data that was written, do you get the value you expect?
Yup - I'm getting the results I expect now that I'm using the more basic IN and OUT commands I created in my custom monitor program. In fact, having been away for a couple of days and come back to it, it seems to be working ok, if sometimes a little intermittently, but I think the PSG isn't totally happy with the reset circuit so I'm going to go away and test that a little more.
In any case, the IO is working so no reason not to expect the sound output to work too (famous last words!) - I've got some work on my hands to get it playing chiptunes, but it's a start.
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Okay, as part of getting the PSG up and running for sound generation, I'm adding a Z80 CTC to the SBC for clocked interrupts and so on. It's mostly connected up now from what few bits of information I can find online, but I'm not sure about IE0 and IE1.
Obviously I'm using an SIO/2 which generates interrupts when characters are received via the serial interface, so daisy-chaining the interrupt according to priority is important and I'm not sure how to wire up these two pins - I can't find any schematics that use a CTC in that way and the datasheets/manuals that I do have for the CTC don't explain how to do this.
I'm off to go read through the documentation in more detail, but thought I'd see if anyone has any advice about how best to integrate the CTC into the design.
EDIT:
Oh, okay, found this which seems to clarify the situation somewhat:
The question is, do I disconnect the ~INT line from the Z80? At the moment it's connected to ~INT on the SIO as per Grant's schematic and pulled high through a 1K resistor. -
in simple terms
IEO & IEI form a daisy chain
There is a time limit on daisy chain length. Memory says 4 Z80 IO chips chained before need to add helper logic.
The device closest to CPU prevents lower devices from interrupting if the device has a pending interrupt.
For Z80 chips like CTC and SIO, intack is generated internal to CTC or SIO
Just so you know
A daisy chain like this can be used when you have many DMA devices.
Your picture is wrong in some points
Redraw it with IEI close to Z80. IEO goes to lesser devices in priority chain.
The Interrupt output of each device chip goes to an OR gate with the output of OR connected to Z80 INT. A logic low OR.
This is a good place to use open collector logic.
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in simple terms
IEO & IEI form a daisy chain
There is a time limit on daisy chain length. Memory says 4 Z80 IO chips chained before need to add helper logic.
Ah no worries about that - I think the CTC and SIO are going to be only peripherals in the interrupt chain, or maybe a PIO or 8255 when I get around to that.The device closest to CPU prevents lower devices from interrupting if the device has a pending interrupt.
Oh? I thought it was the other way around? It would appear the reference http://www.z80.info/1653.htm I was reading was incorrect then (also the source of the daisy chain image.)For Z80 chips like CTC and SIO, intack is generated internal to CTC or SIO
So I don't need to worry about connecting ~INTACK up from the Z80 to the CTC or SIO?Your picture is wrong in some points
Redraw it with IEI close to Z80. IEO goes to lesser devices in priority chain.
Well I think in that image, the DART, PIO and CTC are prioritised in that order. Not my work, but your comments are noted. So you're saying that ~INT from the Z80 goes to IEI of the highest priority device, then its IEO to the next device's IEI and so on until the last device, whose IEO is connected to +5V?The Interrupt output of each device chip goes to an OR gate with the output of OR connected to Z80 INT. A logic low OR.
This is a good place to use open collector logic.
Oh, so IEO for each device is OR'd to Z80 ~INT? Sorry, I'm a bit confused now...
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Let me rewrite what I said
Z80 INT input pin
You connect all interrupt outputs to this pin. To do this you need a OR gate.
Any low input = Low output.
Using Open collector logic you have a wired OR where any output can create a low.
IEI & IEO
This is a separate daisy chain.
You start with first IEI input pulled to +5V. This is Highest end of chain.
You just connect to IEO output to next IEI input.
Nothing else is in this chain but IEI & IEO
All the good stuff is already inside the Z80 IO chips, so you do not need to worry about it with Z80 IO chips until you have a long chain.
+5V to CTC IEI
CTC IEO to SIO IEI
SIO IEO no connection
Z80 Int pin = CTC Int pin OR SIO Int pin
An you are done.
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Let me rewrite what I said
Z80 INT input pin
You connect all interrupt outputs to this pin. To do this you need a OR gate.
Any low input = Low output.
Using Open collector logic you have a wired OR where any output can create a low.
IEI & IEO
This is a separate daisy chain.
You start with first IEI input pulled to +5V. This is Highest end of chain.
You just connect to IEO output to next IEI input.
Nothing else is in this chain but IEI & IEO
All the good stuff is already inside the Z80 IO chips, so you do not need to worry about it with Z80 IO chips until you have a long chain.
+5V to CTC IEI
CTC IEO to SIO IEI
SIO IEO no connection
Z80 Int pin = CTC Int pin OR SIO Int pin
An you are done.
Aha! Crystal clear, C. Thank you!
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So, something like this?
EDIT: Oh wait, the NOR gate is wrong - need an AND gate instead?
0 | 0 = 0
1 | 0 = 0
0 | 1 = 0
1 | 1 = 1 -
I believe that you want an OR gate there.
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I believe that you want an OR gate there.
Really? An OR gate doesn't match the truth table required according to C's previous comments though?Any low input = Low output.
Using Open collector logic you have a wired OR where any output can create a low.
I know C's stated an OR gate is required but what he says after that matches an AND gate...? -
Z80 Int pin = CTC Int pin OR SIO Int pin -
Z80 Int pin = CTC Int pin OR SIO Int pin
Ah yeah, fair point - thanks netdudeuk!
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Right, well that doesn't work - taking a look at the logic tables, either I'm missing something or the circuit needs an AND gate, not an OR gate?
In my case I have two devices attached in the interrupt daisy chain - an SIO and a CTC. I have no issue with how the IEI-IEO daisy chaining works, I've got the IEI for the CTC at +5v, CTC IEO -> SIO IEI and SIO IEO is not connected to anything.
That way, the CTC should take top priority for any interrupts with the SIO taking second place to it.
The ~INT connections from the SIO and CTC need to connect to the ~INT pin on the Z80. Obviously they need to be gated somehow, otherwise (e.g.) the CTC may try to pull the ~INT line low to trigger an interrupt but the SIO will keep it high as it's not needing the CPU's attention.
So the ~INT line to the CPU needs to go low whenever the ~INT pins on either the SIO or CTC go low, or both, but stay high if SIO and CTC ~INT pins are high, like below:
CTC SIO CPU ~INT
0 0 0
1 0 0
0 1 0
1 1 1
That's the truth table for how the ~INT line to the CPU should behave, based on the possible combinations from CTC and SIO ~INT pins. Remembering that ~INT is active LOW (0).
Here's the truth table for an OR gate:
A B OUT
0 | 0 = 0
0 | 1 = 1
1 | 0 = 1
1 | 1 = 1
How does that match what is required by the CPU's ~INT line? In that case, the only time ~INT would be pulled LOW (active) is when BOTH the CTC and SIO are pulling ~INT low?
Am I missing something?
An AND gate truth table, however, matches what is required to make the circuit work:
A B OUT
0 | 0 = 0
0 | 1 = 0
1 | 0 = 0
1 | 1 = 1
So can anyone explain why I'm being told to use an OR gate instead of an AND gate?
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Simple
INT is active low
The logic you want is to OR all interrupt outputs to the Z80 int pin..
Because INT is active low, this is negative logic where A 1 = low voltage and a 0 = high voltage
A Positive logic AND gate is a negative OR gate.
Missed the fine print
Both the SIO and CTC state this about INT pin
Interrupt Request (output, open-drain, active Low).
You can just connect all the int pins.
There is a reason I forgot about Z80 IO INT pins being Open-drain (open-collector).
First is I worked more with big systems where you always had a driver at card connector.
The Second reason is better.
If you want to put your scope on the CTC INT pin and see if it is generating an interrupt.
With the wired connection( all connected) you would see all interrupts not just CTC INT by putting your probe on CTC INT pin.
I like testable circuits, not one that is harder to trouble shoot.
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I hope that you are getting to grips with the Z80 daisy-chained interrupt priority control.
One thing which travel affords is time to mull things over, consequently I had the opportunity to think more about the interface with the AY-3-8912 and faster Z80's. After all I expect nockieboy will not want to halve the speed of his system just to have it make a few squeaks and pops. Unfortunately being away from home and my usual desktop environment makes it harder to draw pretty diagrams to make the ideas a bit more concrete.
It has been suggested that the sound generator could be connected via a PIO/PIA and this is certainly a possibility but it is an extra (large) package to accommodate and the interface brings its own problems. Also, it increases the complexity of the code needed to talk to the sound chip (though, to be fair, this should be a solve once and forget issue).
However it ought to be possible to interface the 3-8912 to a Z80 directly, after all this is a not uncommon problem with modern, faster spins on classic processors - we can buy a faster CPU than in 1980 but the retro interface chips that one might want to use are more often than not unavailable in a more modern guise.
Looking at the timing diagram for the version with wait states it struck me that the \$\small\overline{WAIT}\$ signal is about the right timing for driving the 3-8912 bus control signals to give the necessary set-up and hold times.
However we need to extend the interval that \$\small\overline{WAIT}\$ is active to allow for the typical 500ns pulse that the 3-8912 needs so the first thing we need is a more flexible wait state generator. Some googling and browsing through 7400 series data sheets suggests the 74xx165 parallel to serial shift register can be used as a wait state generator so we'll go with that.
As we are going to finish the 3-8912 read cycle "early" (to allow for the tri-state delay) we need a latch to grab the data and hold it for the Z80 to read. Given the need for a latch we also need a buffer during write cycles so we can activate the latch during a read cycle and the buffer during a write cycle - the 74ACT646 is rather useful in this scenario - it is a bidirectional buffer/register in a single package.
We also need - well, not much actually, just an inverter, plus the two NOR gates that are already in use to generate BC1 and BDIR.
Here is the schematic
\$\small\overline{SELAY}\$ is the active low select signal for an I/O cycle to the PSG, as discussed previously.
There's a big caveat in that I haven't built this so there might be the odd mistake in the diagram but I think that it should work OK. (remember, always, however, the difference between theory and practice )
The timing is as follows (\$\Theta = 8MHz\$)
All of the 3-8912 timing requirements are met with the exception of the data setup time - if we accept that the negative numbers in the Z80 timing information mean that the data is not guaranteed to be stable when \$\small\overline{WR}\$ falls then an 8MHz Z80 might not get it's act together until 10ns before the rising edge of the clock at the end of T2 (TdCr(WRf)-TdD(WRf)IO - 60 - -55ns = 115ns), add in the propagation delay through the 74ACT646 and the data is not guaranteed to be stable at the PSG until pretty much the rising edge of the clock at the end of T2. That edge clocks the data to drive \$\small\overline{WAIT}\$ low and start the bus cycle on the 3-8912, there is an additional delay through the NOR gates before BC1 & BDIR change state so there should be a guaranteed 20ns or so of data set-up time - not officially enough but better than -55ns.
The wait sates can be extended by changing which of the 74ls165 inputs are tied high and which tied low. Up to 7 wait states can be generated to this should be good up to a 14MHz clock for the Z80. Beyond that the wait state generator, at least, will need a rethink.
Enjoy. -
I hope that you are getting to grips with the Z80 daisy-chained interrupt priority control.
Well actually, no... My focus is on getting the CTC up and running currently as a regular interrupt is a key requirement for the PSG to get it playing sound. I had it set up with the OR gate as C outlined previously, but ~INT was low constantly and the SBC wasn't getting past the 'Press <space> to continue...' message as the SIO was unable to get the Z80's attention to read the Rx buffer (presumably).
I haven't, unfortunately, had any time to look at what could be causing the problem since discovering it, but my next step is to check the CTC to see if it's pulling ~INT low all the time and if not, just connect it up to the SIO and Z80 ~INT without the logic gate (and double check all the wiring of course!)
One thing which travel affords is time to mull things over, consequently I had the opportunity to think more about the interface with the AY-3-8912 and faster Z80's. After all I expect nockieboy will not want to halve the speed of his system just to have it make a few squeaks and pops. Unfortunately being away from home and my usual desktop environment makes it harder to draw pretty diagrams to make the ideas a bit more concrete.
Enjoy.
Absolutely awesome - thanks grumpydoc! Looking forward to getting started on the high-speed interface - now it's working at 4MHz, the PSG is on hold until I get the CTC (and by extension, the interrupt system) working. Hopefully will have an update over the weekend if I get some time to test it.
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nockieboy
As stated in outer post INT is active low, you need a negative logic OR gate.
In positive logic this is an AND gate.
grumpydoc
As stated PIO is easy out but has problems, the part I do not like is the bit banging in place of simple read or write..
I would think that most of the time a program would be writing to the 3-8912.
This lead to How fast can the Z80 write to the 3-8912. I see two Z80 IO writes as the fastest ( a set address & write data). With this in mind, The data pins on 3-8912 can take from the Z80 starting IO cycle until just before Z80 starts next IO cycle, spanning the Instruction fetch and refresh..
Does this give enough time for zero Z80 waits?
For read you could do a start read followed by get data as two Z80 instructions or a wait state read.
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nockieboy
As stated in outer post INT is active low, you need a negative logic OR gate.
In positive logic this is an AND gate.
Sorry C, I obviously misunderstood that post. And a 74HCT08 is the one logic chip I don't have.
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For now just connect all the INT pins.
PIO & CTC are open collector so this is allowed.
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For now just connect all the INT pins.
PIO & CTC are open collector so this is allowed.
Sorted - marvellous. The SBC is booting up now with the CTC/SIO interrupt daisy chain setup. Just need to test the CTC in software now to make sure it's working as expected when I get some free time.