Hi,
I designed a motor controller with the smart gate drive IC DRV8320 from TI. After adjusting the gate current to the recommended value (60mA source, 120mA sink for a 11nC Cgd),
I see some ringing that seems pretty good for a normal driven FET with gate resistors, but no especially good for the smart gate drive I think.
The problem I see is, that in the datasheet of the DRV8320 (
https://www.ti.com/lit/ds/symlink/drv8320.pdf?ts=1622551486828&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDRV8320),
a maximum voltage SHx (between the drain and source of the hi-side FET) of +7VDC is specified and I have never seen such a limit in not smart gate driver ICs.
So, do you think I should be worried by what I see and do you know such limits from other gate drivers?
(In the attachment you see the supply voltage (yellow) and the FET output voltage (blue) at 20A motor phase current and in the second picture is the gate voltage. I would like to increase to 40A, but then I will probably be over the limit...)
In the gate voltage measurement, is the vertical scale really 10V? So the usual plateau is at 50 V instead of 5 V? Why would you want the SHx pin to go above the positive rail? If the output voltage does so i would add a snubber or a fast recovery diode to reduce the peak. I did something similar last week, using a rather old-fashioned drive circuit with L9385 and i remember looking at both output edges (turn-on and turn-off).
Regards, Dieter
How is this signal probed?
The measurment is from the high side MOSFET and the gate voltage is 10-12V above the supply with the charge pump to fully turn on the FET.
I measure with a probe with a really short GND connection (1cm wire). I verified with different measurement points and boards, so it should not be a measurement error.
The ringing comes probably from the stray inductance in the MOSFET outputs and from the stray inductance in the gate path and the recovery time of the body diode of around 40ns. But I‘m unsure if this is normal or if I should be conerned
Well, does it affect anything?
- Transient overvoltage of components
- dV/dt or dI/dt limitations of components
- Switching losses
- EMI/RFI emissions
- Does it match expectations (with the modeled switching loop)?
- Was the switching loop modeled at all?
With absolutely no knowledge of your application, it's impossible to say.
For a typical switching application, with EMI handled by filtering, I would be more than happy with that.
Tim
To make really really sure it is not the probe I'd measure using a low-Z passive divider probe. You can make these from a 1k Ohm resistor soldered to a piece of coax and use a 50 Ohm terminator at the oscilloscope's end. The other end of the 1k Ohm resistor is soldered to the DUT and the shield of the coax to ground.
So the upper rail is at 50 V? And the plateau we see in the gate drive is the deadtime?
The 5 V overshoot above the upper rail in the blue trace is within the 7 V margin. In my circuit i added Schottky diodes parallel to the Mosfets to reduce this overshoot. Overshoots on the output falling edge were much worse in my case.
It depends where you put the diodes. If you switch 20 A in 50 nsec, the parasitic inductance of a 10 mm trace will make a 10 V peak. Is that correct? This means the 5 V peak is a reasonable result already, it won't get much better.
Regards, Dieter