It is up to you, finally an arbitrary choice. Larger dI_L means also larger ripple current over the output capacitor, and therefore, larger ripple voltage (because output capacitor has >0 ESR and less than infinite capacitance). With less inductance, the converter runs in DCM even at higher loads, but even that might not be a problem, it's up to you to decide.
30-40% of full load current (not the IC maximum; not the IC current limit) is some kind of sensible default. You can't have too much inductance per se. If the inductor is physically too large, the options to make it smaller is to increase dI_L or increase switching frequency.
It makes absolutely no sense to use the maximum current capability of the IC. The "usual rule of thumb default" is a decent compromise between inductor size, output capacitor size/stress, and transition point from DCM to CCM, maybe by assuming that the load "usually" is more than 40-50% of maximum. Even if the IC is capable of supplying 99999999999A, it does not affect this decision.
It seems someone has just mixed up inductance and saturation current. What you really should do is to look at the pulse-by-pulse current limitation feature of the IC, specifically the worst-case maximum value (which can be significantly more than the rated max I_out), and make sure the inductor does not saturate there, at least fully. If the inductor saturates, it loses inductance, and as a result, the current rise rate will increase, possibly so much that the current limit feature (which turns the FETs off) is too slow to react in time. Unfortunately, the reaction delay is almost never specified, but it tends to be fast enough that losing maybe 50% of inductance won't be a problem. Therefore, with the usual 70% saturation criteria as given in inductor datasheets, there is no need to leave extra margin. Just don't make the mistake to choose an inductor which saturates at 1A "because my load never is over 1A" and then the IC is capable of supplying 2A continuous and worst-case current limit value is at 4A.