00000000 - File Type: DS1000Z
00000010 - Version: 00.04.04.03.02
00000020 - Bitmask: 00000700
00000024 - # Sections: 10
Offset Section Name SectiSz StartAdr CRC32 Type
00000028 /sys/SparrowAPP.out 001045C6 00000280 6E08406C 00000001 [00000280-00104845] CRC OK
00000064 /sys/SparrowFPGA.hex 000C4372 00104846 679334B7 00000005 [00104846-001C8BB7] CRC OK
000000A0 /sys/SparrowDGFPGA.hex 00046F04 001C8BB8 E4FDFCA9 00000006 [001C8BB8-0020FABB] CRC OK
000000DC /sys/logo.hex 000BB818 0020FABC AC2CE5C4 0000000A [0020FABC-002CB2D3] CRC OK
00000118 /sys/guiResData.hex 000B6A2C 002CB2D4 EFF83A4B 0000000C [002CB2D4-00381CFF] CRC OK
00000154 /sys/guiPicData.hex 0001E995 00381D00 C1DBFD83 00000011 [00381D00-003A0694] CRC OK
00000190 /sys/SparrowConfig.hex 000BB818 003A0695 BAD12B30 00000010 [003A0695-0045BEAC] CRC OK
000001CC /sys/SparrowWaveTable.hex 000020E8 0045BEAD B0445B96 0000000B [0045BEAD-0045DF94] CRC OK
00000208 /sys/SparrowCalFile.hex 0002329C 0045DF95 FBE2BA34 0000000F [0045DF95-00481230] CRC OK
00000244 00000118 00481231 6AD11BAE 00000032 [00481231-00481348] CRC OK
Offset CRC32 Flags Filesize Endianes Version Rsvd
00000280 A7E7BDB2 00000003 001045AE AA5555AA 4040302 00000000 [00000298-00104845] CRC OK SparrowAPP.out CRC-PATCH OK
00104846 C9AF5D56 00000000 000C435A AA5555AA 4040302 00000000 [0010485E-001C8BB7] CRC OK
001C8BB8 138E13B9 00000000 00046EEC AA5555AA 4040302 00000000 [001C8BD0-0020FABB] CRC OK
0020FABC 9B4EA177 00000000 000BB800 AA5555AA 4040302 00000000 [0020FAD4-002CB2D3] CRC OK
002CB2D4 D7825E44 00000000 000B6A14 AA5555AA 4040302 00000000 [002CB2EC-00381CFF] CRC OK
00381D00 D34B79C8 00000001 0001E97D AA5555AA 4040302 00000000 [00381D18-003A0694] CRC OK
003A0695 5DEF7058 00000000 000BB800 AA5555AA 4040302 00000000 [003A06AD-0045BEAC] CRC OK
0045BEAD 558BD392 00000000 000020D0 AA5555AA 4040302 00000000 [0045BEC5-0045DF94] CRC OK
0045DF95 7717C897 00000000 00023284 AA5555AA 4040302 00000000 [0045DFAD-00481230] CRC OK
File Processed OK
Did you use the latest firmware version of rigol ds1000z? What is this modification, I do not understand it?
5) Disabled set bandwidth to license maximum on start (BW20 fix)
I can not attach one archive (1MB limit) and multi-volume zip has problems with unpacking. Therefore, the rar archives, renamed to zip, are attached. If anyone knows how to solve this problem by the more correct method - let me know, please.
Images are stock now, original logo and guiPicData which is repacked, why?
What was changed there in last release?
In windows there is no need to rename any files if you use any 3rd party packer...
Is it possible to modify firmware that it will allow use protocol decoders in segmented memory mode (option is greyed out) or maybe even better to decod from whole memory and not just from screen?
Is it possible to modify firmware that it will allow use protocol decoders in segmented memory mode (option is greyed out) or maybe even better to decod from whole memory and not just from screen?
I never understood why Rigol took such an idiotic decision to disable the ability of combining segmented memory and protocol decoding. That's just way too disappointing.
Is it possible to modify firmware that it will allow use protocol decoders in segmented memory mode (option is greyed out) or maybe even better to decod from whole memory and not just from screen?I still studied the decoding protocol modules to a minimum, only in some of the names of functions, associated with LXI. A list of the names of functions of the latest Rigol firmware (with binding to addresses) is available in the plugin archive.
If the decoding is done in the central processor, then there should not be any fundamental problems. As a first step, you need to find the module, write an alternative module, and load it into memory with the utility. When/if it is debugged, you can inject it into the firmware. The work is certainly very large, but really feasible.
If FPGA resources are used for decoding, this will significantly complicate the process. I do not really know the working programs that allow you to "disassemble" the firmware of large FPGAs. To understand all the details of FPGA functioning only on the basis of calls from the firmware is very difficult, if at all possible. This is a typical "blackbox" study.
If the decoding is done in the central processor, then there should not be any fundamental problems.